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da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 1 of 93 ? 2017 dialog semiconductor general description da9062 - a is a power management integrated circuit (pmic) optimized for supplying systems with single - and dual - core processor s, i/o, ddr memory, and peripherals. it targets car navigation, vehicle infotainment systems, automotive telematics and fpga based applications. da9062 - a features four buck converters providing a total current of 8.5 a. high efficiency is achieved over a wide load range by using automatic pulse frequency modulation (pfm) mode. all power switches are integrated; therefore, external schottky diodes are not required. furthermore, low - profile inductors can be used with da9062 - a . two of the buck converters c an be used in a dual - phase configuration, and one can be used as a ddr vtt supply. the f our ldo regulators with programmable output voltage provide up to 300 ma. dynamic voltage control (dvc) allows dynamic control of da9062 - a s upply voltages according to the operating point of the system. it is controlled by writing directly to the registers using the i 2 c compatible 2 - wire interface or the gpios. da9062 - a features a programmable power sequencer that handles start - up and shutdown sequences. power mode transitions can be triggered with software control, gpios, or with the on - key. several types of on - key presses can be detected to trigger different power mode transitions. the real - time clock (rtc) , with an external 32 khz crystal oscillator , provides tim e keeping and alarm functions. additionally, the integrated watchdog timer monitors the system. five gpios are able to perform system functions, including: keypad supervision, application wake up , and timing - controlled external regulators/power switches or other ics. da9062 - a is also available as a consumer and industrial version da906 2 . key features input voltage 2.8 v to 5.5 v four buck converters with dvc : buck1: 0.3 v to 1.57 v, 2.5 a buck2: 0.3 v to 1.57 v, 2.5 a (can be used in dual - phase configuration with buck1) buck3: 0.8 v to 3.34 v, 2 a buck4: 0.53 v to 1.8 v, 1.5 a (can be used as ddr vtt supply) 3 mhz switching frequency (enables low profile inductors) four ldo regulators: ldo1: 0.9 v to 3.6 v, 100 ma ldo2, ldo3, ldo4: 0.9 v to 3.6 v, 300 ma programmable power mode sequencer system supply and junction temperature monitoring watchdog timer five gpios coin cell/super - capacitor charger ultra - low power rtc with alarm 32 khz oscillator with external crystal - 40 c to + 12 5 c juncti on temperature range 40 - pin qfn 6 mm 6 mm package, 0.5 mm pitch (exposed paddle) a utomotive aec - q100 grade 2 ( - 40 c to 105 c) applications car navigation systems in - car infotainment t elematics s ingle core application processors fpgas
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 2 of 93 ? 2017 dialog semiconductor block diagram figure 1 : da9062 - a block diagram b u c k 1 b u c k 2 b u c k 3 b u c k 4 l b u c k 4 l b u c k 3 l b u c k 2 l b u c k 1 c b u c k 1 c b u c k 2 c b u c k 3 c b u c k 4 g p i o 3 2 k h z o s c i l l a t o r w d r t c p o w e r s e q u e n c e r i n t e r r u p t c o n t r o l 2 - w i r e i n t e r f a c e c o n t r o l a n d s t a t u s r e g i s t e r s d a 9 0 6 2 - a g p i o 0 g p i o 1 g p i o 2 n o n k e y n r e s e t r e q n i r q n r e s e t v r e f s d a v d d _ b u c k 1 v d d _ b u c k 2 v d d _ b u c k 3 v d d _ b u c k 4 b b a t c h a r g e r c v b b a t + - v b b a t g p i o 3 g p i o 4 v d d c o r e c l d o c o r e s c l x t a l _ i n x t a l _ o u t c v r e f t p l d o 4 c l d o 4 l d o 3 c l d o 3 v d d _ l d o 3 4 l d o 2 c l d o 2 v d d _ l d o 2 l d o 1 c l d o 1 v s y s i r e f v d d i o r i r e f ( v t t ) o p t i o n a l
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 3 of 93 ? 2017 dialog semiconductor contents general description ................................ ................................ ................................ ............................ 1 key features ................................ ................................ ................................ ................................ ........ 1 applications ................................ ................................ ................................ ................................ ......... 1 block diagram ................................ ................................ ................................ ................................ ..... 2 contents ................................ ................................ ................................ ................................ ............... 3 1 package infor mation ................................ ................................ ................................ ..................... 6 1.1 pin list ................................ ................................ ................................ ................................ ... 6 1.2 package outline drawing ................................ ................................ ................................ ...... 8 2 absolute maximum rating s ................................ ................................ ................................ ......... 9 3 recommended operating conditions ................................ ................................ ......................... 9 4 electrical characteristics ................................ ................................ ................................ ........... 10 4.1 digital i/o ................................ ................................ ................................ ............................ 10 4.2 watchdog ................................ ................................ ................................ ............................ 11 4.3 2 - wire interface ................................ ................................ ................................ ................... 11 4.4 ldos ................................ ................................ ................................ ................................ ... 13 4.4.1 ldo1 ................................ ................................ ................................ .................... 13 4.4.2 ldo2, ldo3, ldo4 ................................ ................................ ............................. 14 4.4.3 ldo core ................................ ................................ ................................ ........... 15 4.5 buck converters ................................ ................................ ................................ .................. 16 4.5.1 buck1, buck2 ................................ ................................ ................................ ....... 16 4.5.2 buck3 ................................ ................................ ................................ ................... 18 4.5.3 buck4 ................................ ................................ ................................ ................... 20 4.6 backup battery charger ................................ ................................ ................................ ...... 23 4.7 32 khz crystal oscillator ................................ ................................ ................................ ..... 23 4.8 internal oscillator ................................ ................................ ................................ ................ 24 4.9 system supply voltage supervision ................................ ................................ ................... 24 4.10 junction temperature supervision ................................ ................................ ..................... 25 4.11 current consumption ................................ ................................ ................................ .......... 25 5 typical characteristics ................................ ................................ ................................ ............... 26 6 system block diagram ................................ ................................ ................................ ............... 29 6.1 ddr power management ................................ ................................ ................................ ... 30 7 functional description ................................ ................................ ................................ ............... 31 7.1 control signals ................................ ................................ ................................ .................... 31 7.1.1 nonkey ................................ ................................ ................................ .............. 31 7.1.2 nresetreq ................................ ................................ ................................ ....... 31 7.1.3 nreset ................................ ................................ ................................ ............... 32 7.1.4 nirq ................................ ................................ ................................ ..................... 32 7.2 2 - wire interface ................................ ................................ ................................ ................... 32 7.2.1 register map paging ................................ ................................ ........................... 33 7.2.2 details of the 2 - wire protocol ................................ ................................ .............. 33 7.3 gpios ................................ ................................ ................................ ................................ .. 35 7.3.1 gpi functionality ................................ ................................ ................................ . 36 7.3.2 gpo functionality ................................ ................................ ................................ 37
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 4 of 93 ? 2017 dialog semiconductor 7.3.3 alternate functions ................................ ................................ .............................. 37 7.3.4 gpio forwarding ................................ ................................ ................................ . 38 7.3.5 analog functions ................................ ................................ ................................ . 38 7.4 dynamic voltage control ................................ ................................ ................................ .... 38 7.5 regulator voltage a and b selection ................................ ................................ .................. 38 7.6 ldos ................................ ................................ ................................ ................................ ... 39 7.6.1 control ................................ ................................ ................................ ................. 39 7.6.2 current limit ................................ ................................ ................................ ........ 39 7.6.3 output pull - down ................................ ................................ ................................ . 39 7.7 switching regulators ................................ ................................ ................................ .......... 40 7.7.1 control ................................ ................................ ................................ ................. 40 7.7.2 output voltage slewing ................................ ................................ ....................... 40 7.7.3 soft - start ................................ ................................ ................................ .............. 40 7.7.4 active discharge ................................ ................................ ................................ .. 40 7.7.5 peak current limit ................................ ................................ ............................... 40 7.7.6 operating mode ................................ ................................ ................................ ... 41 7.7.7 half - current mode ................................ ................................ ............................... 41 7.7.8 buck1 and buck2 in dual - phase mode ................................ ............................... 41 7.7.9 buck4 in ddr memory bus termination mode ................................ ................... 41 7.8 power modes ................................ ................................ ................................ ...................... 42 7.8.1 no - power mode ................................ ................................ ............................... 43 7.8.2 rtc mode ................................ ................................ ................................ ........... 43 7.8.3 reset mode ................................ ................................ ................................ ....... 43 7.8.4 pow erdown mode ................................ ................................ .......................... 44 7.8.5 power - up, power - down, and shutdown sequences ................................ .......... 45 7.8.6 active mode ................................ ................................ ................................ ...... 45 7.9 power supply sequencer ................................ ................................ ................................ .... 46 7.9.1 sub - sequences ................................ ................................ ................................ ... 47 7.9.2 regulator control ................................ ................................ ................................ . 47 7.9.3 gpo control ................................ ................................ ................................ ........ 48 7.9.4 wait step ................................ ................................ ................................ ............. 49 7.9.5 32 khz clock output ................................ ................................ ............................ 49 7.9.6 power - down disable ................................ ................................ ........................... 49 7.10 junction temperature supervision ................................ ................................ ..................... 49 7.11 system supply voltage supervision ................................ ................................ ................... 49 7.12 backup battery charger ................................ ................................ ................................ ...... 50 7.13 real - time clock ................................ ................................ ................................ .................. 50 7.13.1 32 khz crystal oscillator ................................ ................................ ..................... 50 7.14 internal oscillator ................................ ................................ ................................ ................ 51 7.15 watchdog ................................ ................................ ................................ ............................ 51 8 register map ................................ ................................ ................................ ................................ 52 8.1 register page control ................................ ................................ ................................ ......... 52 8.2 overview ................................ ................................ ................................ ............................. 52 9 application information ................................ ................................ ................................ .............. 55 9.1 component selection ................................ ................................ ................................ .......... 55 9.1.1 resistors ................................ ................................ ................................ .............. 55 9.1.2 capacitors ................................ ................................ ................................ ............ 55
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 5 of 93 ? 2017 dialog semiconductor 9.1.3 ind uctors ................................ ................................ ................................ .............. 56 9.1.4 crystal ................................ ................................ ................................ .................. 56 9.1.5 backup battery ................................ ................................ ................................ .... 57 9.2 pcb layout ................................ ................................ ................................ ......................... 57 9.2.1 general recommendations ................................ ................................ ................. 58 9.2.2 ldos and switched mode supplies ................................ ................................ .... 58 9.2.3 32 khz crystal oscillator ................................ ................................ ..................... 58 9.2.4 optimizing thermal performance ................................ ................................ ........ 58 10 ordering information ................................ ................................ ................................ .................. 59 appendix a register descripti ons ................................ ................................ ................................ .. 60 a.1 page 0 ................................ ................................ ................................ ............................... 60 a.1.1 page control ................................ ................................ ................................ ........ 60 a.1.2 power manager control and monitoring ................................ .............................. 60 a.1.3 irq e vents ................................ ................................ ................................ .......... 61 a.1.4 irq masks ................................ ................................ ................................ ........... 62 a.1.5 system control ................................ ................................ ................................ .... 63 a.1.6 gpio control ................................ ................................ ................................ ....... 66 a.1.7 power supply control ................................ ................................ .......................... 69 a.1.8 rtc calendar and alarm ................................ ................................ .................... 74 a.2 page 1 ................................ ................................ ................................ ............................... 77 a.2.1 power supply sequencer ................................ ................................ .................... 77 a.2.2 power supply contro l ................................ ................................ .......................... 82 a.2.3 bbat charger control ................................ ................................ ......................... 86 a.3 page 2 ................................ ................................ ................................ ............................... 87 a.3.1 customer trim and configuration ................................ ................................ ....... 87 a.3.2 customer device specific ................................ ................................ .................... 90
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 6 of 93 ? 2017 dialog semiconductor 1 package information 1.1 pin list table 1 : da9062 - a pin description pin no. pin name t ype table 2 description paddle gnd gnd power grounds of the buck s, digital ground 1 vldo1 ao ldo1 output voltage 2 vldo2 ao ldo2 output voltage 3 vdd_ldo2 ps ldo2 supply 4 iref ao reference current 5 vref aio reference voltage 6 xtal_in ai crystal connection 7 vss_ana gnd analog ground 8 xtal_out ao crystal connection 9 vldo3 ao ldo3 output voltage 10 vdd_ldo34 ps ldo3 and ldo4 supply 11 vldo4 ao ldo4 output voltage 12 vbbat ao backup battery connection 13 sda dio data signal of the 2 - wire interface 14 scl di clock signal of the 2 - wire interface 15 nonkey di input for power - on key 16 nresetreq di reset request input 17 vlx_buck4 ao switching node of buck4 18 vdd_buck4 ps buck4 supply 19 vdd_buck3 ps buck3 supply 20 vlx_buck3 ao switching node of buck3 21 gpio0 dio general purpose i/o, vddq reference, wdkick 22 gpio1 dio general purpose i/o, vttr 23 vddio ps io supply 24 vbuck4 ai voltage feedback of buck4 25 vbuck3 ai voltage feedback of buck3 26 vbuck1 ai voltage feedback of buck1 27 vbuck2 ai voltage feedback of buck2 28 gpio2 dio general purpose i/o, pwr_en 29 gpio3 dio general purpose i/o 30 gpio4 dio general purpose i/o, sys_en 31 vlx_buck1 ao switching node of buck1 32 vdd_buck1 ps buck1 supply 33 vdd_buck2 ps buck2 supply
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 7 of 93 ? 2017 dialog semiconductor pin no. pin name t ype table 2 description 34 vlx_buck2_a ao switching node of buck2 35 vlx_buck2_b ao switching node of buck2 36 tp dio test pin 37 nirq do interrupt signal to host processor 38 nreset do reset output 39 vddcore ao internal supply 40 vsys ps system supply, ldo1 supply table 2 : pin type definition pin type description pin type description di digital input ai analog input do digital output ao analog output dio digital input/output aio analog input/output ps power supply gnd ground connection
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 8 of 93 ? 2017 dialog semiconductor 1.2 package outline drawing figure 2 : da9062 - a package outline drawing min 0.20 min 0.20
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 9 of 93 ? 2017 dialog semiconductor 2 absolute maximum ratings table 3 lists the absolute maximum ratings of the device. exceeding these ratings may cause permanent damage to the device. d evice f unctionality is only guaranteed under the conditions listed in sect ions 3 and 4 . operating the device in co nditions exceeding those listed in s ections 3 and 4 , bu t compli ant with the absolute maximum ratings listed in table 3 , for extended periods of time may affect device reliability. table 3 : absolute maximum ratings parameter symbol note min typ max unit storage temperature - 6 5 +150 c junction temperature t j - 40 + 150 note 1 c supply voltage v sys - 0.3 5.5 v all other pins - 0.3 v sys + 0.3 note 2 v esd protection hbm v esd_hbm 2000 v esd protection cdm v esd_cd m corner pins 750 v all other pins 500 note 1 see sections 4.10 and 7.10 for more details. note 2 voltage must not exceed 5.5 v. 3 recommended operating conditions table 4 : recommended operating conditions parameter symbol note min typ max unit o perating junction temperature t j - 40 + 125 c supply voltage v sys 0 5.5 v supply voltage io v ddio io supply voltage note 1 1.2 3.6 v maximum power dissipation note 2 p diss derating factor above t a = 70 c: 56 mw/ c 3000 mw note 1 v ddio must not exceed v sys . note 2 obtained from package thermal simulation, board dimension 76 mm x 114 mm x 1.6 mm (jedec), 6 - layer board, 35 m thick copper top/bottom layers, 17 m thick copper inside layers, natural convection (still a ir).
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 10 of 93 ? 2017 dialog semiconductor 4 electrical characteristics 4.1 digital i/o unless otherwise noted, the following is valid for t j = - 40 c to + 12 5 oc, v sys = 2.8 v to 5.5 v . table 5 : digital i/o electrical characteristics parameter symbol test conditions min typ max unit input high voltage (gpi0 - gpi4, nresetreq) v ih vddcore mode 1.0 v sys v vddio mode 0.7 * v ddio v sys input low voltage (gpi0 C gpi4, nresetreq) v il vddcore mode - 0.3 0.4 v vddio mode - 0.3 0.3 * v ddio input high voltage (nonkey) v ih rtc mode 1.0 v sys v vddcore mode 1.0 v sys vddio mode 0.7 * v ddio input low voltage (nonkey) v il rtc mode - 0.3 0.4 v vddcore mode - 0.3 0.4 vddio mode - 0.3 0.3 * v ddio input high voltage (scl, sda) v ih vddcore mode 1.0 v vddio mode 0.7 * v ddio input low voltage (scl, sda) v il vddcore mode 0. 4 v vddio mode 0.3 * v ddio output high voltage (gpo0 C gpo4, nreset, nirq) v oh i load = 1 ma push - pull mode 0.7 * v ddio v output low voltage (gpo0 C gpo4, nreset, nirq) v ol i load = 1 ma 0.3 v output low voltage (sda) v ol i load = 20 ma 0.4 v i load = 3 ma 0.24 source current capability (gpo0 C gpo4) i oh v o ut = 0.7 * v ddio v ddio 1.8 v - 1 ma sink current capability (gpo0 C gpo4) i ol v o ut = 0.3 v 1 ma input capacitance (scl, sda) c in 10 pf pull - down resistance (gpi0 C gpi4) r pd 50 100 250 k pull - up resistance (gpo0 C gpo4) r pu v ddio = 1.5 v 60 180 310 k ? v ddio = 1.8 v 45 120 190 v ddio = 3.3 v 2 0 40 60
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 11 of 93 ? 2017 dialog semiconductor 4.2 watchdog unless otherwise noted, the following is valid for t j = - 40 c to + 12 5 oc , v sys = 2.8 v to 5.5 v . table 6 : watchdog electrical characteristics parameter symbol test conditions min typ max unit minimum watchdog time t wdmin external 32 khz oscillator 110 ms internal 25 khz oscillator 200 ms maximum watchdog time t wdmax external 32 khz oscillator 2 s internal 25 khz oscillator 2.5 s minimum assert time of wdkick t wdkickmin 150 s 4.3 2 - wire interface figure 3 : 2 - wire interface timing s t o p s d a s c l t f t r t f s t a r t t h _ s t a t h _ d 1 / f s c l v i h v i l v i h v i l t s u _ d t l o w t h i g h t v d _ d a c k t v d _ a c k t s u _ s t o
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 12 of 93 ? 2017 dialog semiconductor unless otherwise noted, the following is valid for t j = - 40 c to + 12 5 oc , v sys = 2.8 v to 5.5 v . table 7 : 2 - wire interface electrical characteristics parameter symbol test conditions min typ max unit bus free time stop to start t buf 0.5 s bus line capacitive load c b 150 pf standard/fast/fast+ mode scl clock frequency f scl note 1 0 1000 khz start condition set - up time t su_sta 0.26 s start condition hold time t h_sta 0.26 s scl low time t w_cl 0.5 s scl high time t w_ch 0.26 s 2 - wire scl and sda rise time t r (input requirement) 1000 ns 2 - wire scl and sda fall time t f (input requirement) 300 ns data set - up time t su_d 50 ns data hold - time t h_d 0 ns data valid time t vd_d 0.45 s data valid time acknowledge t vd_ack 0.45 s stop condition set - up time t su_sto 0.26 s high speed mode scl clock frequency f scl requires v ddio 1.8 v note 1 0 3400 khz start condition set - up time t su_sta 160 ns start condition hold time t h_sta 160 ns scl low time t w_cl 160 ns scl high time t w_ch 60 ns 2 - wire scl and sda rise time t r (input requirement) 160 ns 2 - wire scl and sda fall time t f (input requirement) 160 ns data set - up time t su_d 10 ns data hold - time t h_d 0 ns stop condition set - up time t su_sto 160 ns note 1 minimum clock frequency is 10 khz if 2wire_to is enabled .
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 13 of 93 ? 2017 dialog semiconductor 4.4 ldos 4.4.1 l do 1 unless otherwise noted, the following is valid for t j = - 40 c to + 12 5 oc . table 8 : ldo1 electrical charac t eristics parameter symbol test conditions min typ max unit input voltage v dd v dd = v sys (internally connected) 2.8 5.5 v maximum o utput current i out_max 100 ma output voltage v ldo programmable in 50 mv steps 0.9 3.6 v output accuracy i out = i o ut_ max including static line / load regulation - 3% +3% stabili z ation capacitor c out including voltage and temperature coefficient - 55% 1.0 +35% f output capacitor esr r c out _esr f > 1 mhz including wiring parasitics 0 3 00 m ? short circuit current i short 200 ma dropout voltage v dropout v ldo = 3.3 v i out = i o ut_max 100 150 mv static line regulation v s _ line v dd = 3.0 v to 5.5 v i out = i o ut_ max 5 20 mv static lo ad regulation v s _ load i out = 1 ma to i o ut_ max 5 20 mv line transient response v tr _ line v dd = 3.0 v to 3.6 v i out = i o ut_ max tr = tf = 10 s 5 20 mv load transient response v tr _ load v dd = 3.6 v , v ldo = 3.3 v i out = 1 ma to i o ut_ max tr = tf = 1 s 30 50 mv power supply rejection ratio psrr v dd = 3.6 v v dd - v ldo 0.6 v i out = i o ut_ max /2 f = f vdd _ ldo f = 10 hz to 10 khz 40 60 db output noise n v dd = 3.6 v , v ldo = 2.8 v i out = 5 ma to i o ut_ max f = 10 hz to 100 khz t a = 25 oc 70 v rms quiescent current in on mode i q _ on t a = 25 oc 9 + 0.9% i out a quiescent current in sleep mode i q _ sleep t a = 25 oc 1.5 + 1.6% i out a quiescent current in off mode i q _ off v ldo < 0.5 v t a = 25 oc 1 a turn - on time t on 10 % to 90 % 350 s sleep mode 450 turn - off t ime t off 90 % to 10% pull - down enabled 1 ms
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 14 of 93 ? 2017 dialog semiconductor parameter symbol test conditions min typ max unit pull - down resistance in off mode r off v ldo = 0.5 v can be disabled via ldo1_pd_dis 100 4.4.2 l do 2, l do 3, l do 4 unless otherwise noted, the following is valid for t j = - 40 c to + 12 5 oc . table 9 : ldo2, ldo3, ldo4 electrical characteristics parameter symbol test conditions min typ max unit input voltage v dd v dd = v sys 2.8 5.5 v s upplied from buck converter 1.5 maximum o utput current i out_max v dd 1.8 v ( i out = i o ut_ max /3 v dd < 1. 8 v ) 300 ma output voltage v ldo programmable in 50 mv steps 0.9 3.6 v output accuracy i out = i o ut_ max including static line / load regulation - 3% +3% stabili z ation capacitor c out including voltage and temperature coefficient - 55% 2.2 +35% f output capacitor esr r c out _esr f > 1 mhz including wiring p arasitic s 0 3 00 m ? short circuit current i short 600 ma dropout voltage v dropout i out = i o ut_max ( v dd < 1. 8 v i out = i o ut_ max /3 ) note 1 100 150 mv static line regulation v s _ line v dd = 3.0 v to 5.5 v i out = i o ut_ max 5 20 mv static load regulation v s _ load i out = 1 ma to i o ut_ max 5 20 mv line transient response v tr _ line v dd = 3.0 v to 3.6 v i out = i o ut_ max t r = t f = 10 s 5 20 mv load transient response v tr _ load v dd = 3.6 v i out = 1 ma to i o ut_ max t r = t f = 1 s 30 50 mv power supply rejection ratio psrr v dd = 3.6 v v dd - v ldo 0.6 v i out = i o ut_ max /2 f = f vdd _ ldo f = 10 hz to 1 khz f = 1 khz to 10 khz f = 10 khz to 100 khz 70 60 40 8 0 7 0 5 0 db output noise n v dd = 3.6 v , v ldo = 2.8 v i out = 5 ma to i o ut_ max f = 10 hz to 100 khz 50 v rms
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 15 of 93 ? 2017 dialog semiconductor parameter symbol test conditions min typ max unit quiescent current in on mode i q _ on t a = 25 oc 9 + 0.34% i out a quiescent current in sleep mode i q _ sleep t a = 25 oc 2 + 0.7% i out a quiescent current in off mode i q _ off v ldo < 0.5 v t a = 25 oc 1 a turn - on time t on 10 % to 90 % 200 s sleep mode 300 turn - off time t off 90 % to 10 % pull - down enabled 1 ms pull - do wn resistance in off mode r off v ldo = 0.5 v can be disabled via ldo _pd_dis 100 note 1 at v dd = 1.8 v, the dropout voltage at i out_max increases by 70%. 4.4.3 l docore unless otherwise noted, the following is valid for t j = - 40 c to + 12 5 oc , v sys = 2.8 v to 5.5 v . table 10 : ldocore electrical characteristics parameter symbol test conditions min typ max unit output voltage v ddcore note 1 2.45 2.5 2.55 v reset mode 2.2 v stabilization capacitor c out including voltage and temperature coefficient - 55% 2.2 +35% f output capacitor esr r c out _esr f > 1 mhz including wiring p arasitic s 0 300 m ? dropout voltage v dropout no te 2 50 100 mv note 1 setting v dd_fault_lower 2.65 v avoids ldocore dropout, see section 4.9 . note 2 the ldocore supply, vsys, must be maintained above v ddcore + v dropout . note ldocore is only used to supply internal circuits.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 16 of 93 ? 2017 dialog semiconductor 4.5 buck converters 4.5.1 buck1, buck2 unless otherwise noted, the following is valid for t j = - 40 c to + 12 5 oc . table 11 : buck1, buck2 electrical characteristics parameter symbol test conditions min typ max unit input voltage v dd v dd = v sys 2.8 5.5 v output capacitor c out half - current mode including voltage and temperature coefficient - 50% 2 * 22 +30% f full - current mode including voltage and temperature coefficient - 50% 2 * 47 +30% output capacitor esr r c out_ esr c out = 2 * 22 f f > 100 khz including wiring parasitics 15 50 m ? c out = 2 * 47 f f > 100 khz including wiring parasitics 7.5 25 inductor value l buck i ncluding current and temperature dependence 0. 7 1.0 1.3 h inductor resistance r l_dcr 55 100 m ? pwm mode output voltage v buck programmable in 10 mv steps note 1 0. 3 1.57 v output voltage accuracy v buck_acc v dd = 4.2 v , v buck = 1.03 v excluding static line/load regulation and voltage ripple t a = 2 5 oc - 1 +1 % including static line / load regulation and voltage ripple note 2 - 3 +3 transient load regulation v tr _ load v dd = 3.6 v , v buck = 1. 15 v i out = 200 ma to 1000 ma di/dt = 3 a/s l = 1 h 30 45 mv transient line regulation v tr _ line v dd = 3.0 v to 3.6 v i out = 500 ma t r = t f = 10 s 0.2 3 mv output current i out half - current mode 1250 ma f ull - current mode 2500 current limit i lim half - current mode c ontrolled in buck < x > _ilim in 100 ma steps 700 2200 ma full - current mode c ontrolled in buck < x >_ ilim in 200 ma steps 1400 4400 current limit accuracy i lim_acc - 20 % 20 %
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 17 of 93 ? 2017 dialog semiconductor parameter symbol test conditions min typ max unit quiescent current in off mode i q _ off 1 a quiescent current in pwm mode i q _ on half - current mode v dd = 3.6 v i out = 0 ma t a = 2 5 oc 9 ma full - current mode v dd = 3.6 v i out = 0 ma t a = 2 5 oc 11 switching frequency note 3 f osc_frq = 0000 2.85 3 3.15 mhz switching duty cycle dc 14 % 83 % turn - on time t on v buck = 1.15 v buck_slowstart = disabled slew_rate = 10 mv/ 1 s buck _ilim = 1500 ma 0.37 1.2 ms output pull - down resistance r pd v buck = 0.5 v disabled via buck < x > _pd_dis 100 200 pmos on resistance r pmos half - current mode i ncluding pin and routing v dd = 3.6 v 160 m full - current mode i ncluding pin and routing v dd = 3.6 v 80 nmos on resistance r nmos half - current mode i ncluding pin and routing v dd = 3.6 v 60 m full - current mode i ncluding pin and routing v dd = 3.6 v 30 pfm mode output voltage v buck _pfm programmable in 10 mv steps 0.3 1.57 v mode transition current threshold (pfm to pwm) in auto mode i auto_thr v dd = 3.6 v , v buck = 1.15 v r track ? 45 m ? including bondwire, pcb, inductor esr 400 ma output current i out _pfm f orced pfm mode 300 ma current limit i lim _pfm 1000 ma quiescent current i q _ pfm f orced pfm mode i out = 0 ma 27 32 a auto mode i out = 0 ma 35 42 m ode transition time t auto auto mode 6 s note 1 if control buck_mode = 10 ( synchronous) then the buck operates in pfm mode for vbuck < 0.7 v. for complete control of the buck mode (pwm ver sus pfm) use buck_mode = 00 . note 2 minimum tolerance 35 mv. note 3 generated from internal 6 mhz oscillator and can be adjusted by 10 % via control osc_frq, s ee section 7.14 .
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 18 of 93 ? 2017 dialog semiconductor 4.5.2 buck3 unless otherwise noted, the following is valid for t j = - 40 c to + 12 5 oc . table 12 : buck3 electrical characteristics parameter symbol test conditions min typ max unit input voltage v dd v dd = v sys i out 1.5 a 2.8 5.5 v v dd = v sys i out > 1.5 a 3.3 5.5 output capacitor c out i out 1.5 a i ncluding voltage and temperature coefficient - 50% 2 * 22 +30% f i out > 1.5 a i ncluding voltage and temperature coefficient - 50% 2 * 47 +30% output capacitor esr r c out_ esr c out = 2 * 22 f f > 100 khz including wiring parasitics 15 50 m ? c out = 2 * 47 f f > 100 khz including wiring parasitics 7.5 25 inductor value l buck including current and temperature dependence 0. 7 1.0 1.3 h inductor resistance r l_dcr 55 100 m ? pwm mode output voltag e v buck programmable in 2 0 mv steps 0.8 3.34 v output voltage accuracy v buck_acc including static line and load regulation and voltage ripple note 1 - 3 % + 3 % transient load regulation v tr _ load v dd = 3.6 v , v buck = 1.8 v i out = 200 ma to 1 000 ma di/dt = 3 a/s l = 1 h 30 45 mv v dd = 3.6 v , v buck = 1.8 v i out = 200 to 2000 ma di/dt = 3 a/s l = 1 h 60 90 v dd = 5.0 v , v buck = 3.34 v i out = 200 ma to 2000 ma di/dt = 3 a/s l = 1 h 60 90 transient line regulation v tr _ line v dd = 3.0 v to 3.6 v i out = 500 ma tr = tf = 10 s 0.2 3 mv output current i out v dd - v buck 1.25 v 2000 ma v dd - v buck 1.00 v 1250 v dd - v buck 0.75 v 900 current limit i lim controlled in buck 3_ilim in 100 ma steps 1700 3200 ma current limit accuracy i lim_acc - 20% 20%
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 19 of 93 ? 2017 dialog semiconductor parameter symbol test conditions min typ max unit quiescent current in off mode i q _ off 1 a quiescent current in pwm mode i q _ on i out = 0 ma t a = 25 oc 9 ma switching frequency note 1 f osc_frq = 0000 2.85 3 3.15 mhz switching duty cycle dc 15% 100% turn - on time t on v buck = 1.8 v buck_slowstart = disabled slew_rate = 20 mv/ 2 s buck3_ilim = 2500 ma 0.44 1.5 ms output pull - down resistance r pd v buck = 0.5 v disabled via buck3 _pd_dis 100 200 pmos on resistance r pmos including pin and routing v dd = 3.6 v 150 m nmos on resistance r nmos including pin and routing v dd = 3.6 v 60 m pfm mode output voltage v buck _pfm programmable in 2 0 mv steps 0. 8 3.34 v mode transition current threshold (pfm to pwm) in auto mode i auto_thr v dd = 3.6 v , v buck = 1. 8 v r track ? 45 m ? including bondwire, pcb, inductor esr 400 ma output current i out _pfm f orced pfm mode 300 ma current limit i lim _pfm 1000 ma quiescent current i q _ pfm forced pfm mode i out = 0 ma 22 25 a auto mode i out = 0 ma 30 35 mode transition time t auto auto mode 6 s note 1 minimum tolerance 35 mv. note 2 generated from internal 6 mhz oscillator and can be adjusted by 10 % via control osc_frq, see section 7.14 .
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 20 of 93 ? 2017 dialog semiconductor 4.5.3 buck4 unless otherwise noted, the following is valid for t j = - 40 c to + 12 5 oc . table 13 : buck4 electrical characteristics parameter symbol test conditions min typ max unit input voltage v dd v dd = v sys 2.8 5.5 v output capacitor c out including volt age and temperature coefficient - 50% 2 * 22 +30% f output capacitor esr r c out_ esr f > 100 khz including wiring parasitics 15 50 m ? inductor value l buck including current and temperature dependence 0. 7 1.0 1.3 h inductor resistance r l_dcr 55 100 m ? pwm mode output voltage v buck programmable in 10 mv steps note 1 0.53 1.8 v output voltage accuracy v buck_acc including static line/load regulation and voltage ripple note 1 - 3 % + 3 % transient load regulation v tr _ load v dd = 3.6 v , v buck = 1. 35 v i out = 200 ma to 1 0 00 ma di/dt = 3 a/s l = 1 h 25 40 mv v dd = 3.6 v , v buck = 1. 35 v i out = 200 ma to 1 5 00 ma di/dt = 3 a/s l = 1 h 40 60 transient line regulation v tr _ line v dd = 3.0 v to 3.6 v i out = 500 ma t r = t f = 10 s 0.2 3 mv output current i out v dd - v buck 1.25 v 15 00 ma v dd - v buck 1.00 v 1250 current limit i lim controlled in buck 4 _ilim in 100 ma steps 700 2200 ma current limit accuracy i lim_acc i lim = 700 ma to 1400 ma - 15 % + 25 % i lim = 1400 ma to 2200 ma - 10% +15% quiescent current in off mode i q _ off 1 a quiescent current in pwm mode i q _ on i out = 0 ma t a = 25 oc 9 ma switching frequency note 2 f osc_frq = 0000 2.85 3 3.15 mhz switching duty cycle dc 14% 83% turn - on time t on v buck = 1.35 v buck_slowstart = disabled slew_rate = 10 mv/1 s buck4 _ilim = 1500 ma 0.39 1.2 ms output pull - down resistance r pd v buck = 0.5 v disabled via buck4_pd_dis 100 200
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 21 of 93 ? 2017 dialog semiconductor parameter symbol test conditions min typ max unit pmos on resistance r pmos including pin and routing v dd = 3.6 v 150 m ? nmos on resistance r nmos including pin and routing v dd = 3.6 v 60 m ? pfm mode output voltage v buck_pfm programmable in 10 mv steps. 0.53 1.8 v mode transition current threshold (pfm to pwm) in auto mode i auto_thr v dd = 3.6 v , v buck = 1. 35 v r track ? 45 m ? including bondwire, pcb, inductor esr 400 ma output current i out_pfm 300 ma current limit i lim _pfm 1000 ma quiescent current i q _ pfm forced pfm mode i out = 0 ma 22 25 a auto mode i out = 0 ma 30 35 mode tran sition time t auto auto mode 6 s vtt mode input voltage v dd 2.8 5.5 v output capacitor c out including voltage and temperature coefficient - 50% 2 * 47 +30% f output capacitor esr r c out_ esr f > 100 khz including wiring parasitics 7.5 25 m ? inductor value l buck 0.25 h inductor resistance r l_dcr 80 120 m ? output voltage v buck v buck = v ddq /2 0. 675 1.3 v output voltage accuracy v buck _acc relative to vttr i ncluding static line/load regulation and voltage ripple . - 3 % + 4 % output current i out v buck = 0.675 v 4 50 ma v buck = 0.700 v 5 50 v buck = 0.75 0 v 700 transient load regulation v tr _ load v dd = 3.6 v , v buck = 0.675 v i out = +10 ma to +1.0 a i out = - 450 ma to - 10 ma di /dt = 3 a/ s l = 0.25 h 25 40 mv v dd = 3.6 v , v buck = 0.675 v i out = +1 a to +10 ma i out = - 10 ma to - 450 ma di /dt = 3 a/ s l = 0.25 h 35 50 v dd = 3.6 v , v buck = 0.75 v i out = +10 ma to +1.0 a i out = - 700 ma to - 10 ma di /dt = 3 a/ s l = 0.25 h 25 40
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 22 of 93 ? 2017 dialog semiconductor parameter symbol test conditions min typ max unit v dd = 3.6 v v buck = 0. 75 v i out = +1 a to +10 ma i out = - 10 ma to - 700 ma di /dt = 3 a/ s l = 0.25 h 35 50 turn - on time t on v buck = 0.75 v buck_slowstart = disabled slew_rate = 10 mv/1 s buck4 _ilim = 1500 ma 0.33 1.2 ms vtt r buffer feedback voltage v ddq 1.35 2.6 v vttr output voltage v ttr v ttr = v ddq /2 0.675 1.3 v vttr voltage accuracy v ttr_acc relative to v ddq input voltage - 49 % + 5 1 % vttr output capacitor c vttr including volt age and temperature coefficient - 50% 0.1 +30% f vttr output current i vtt r sink/source - 10 +10 ma note 1 if control buck4_mode = 10 ( synchronous) then the buck operates in pfm mode for vbuck < 0.7 v. for complete control of the buck mode (pwm v ersus pfm) use buck4_mode = 00 . note 2 minimum tolerance 35 mv. note 3 generated from internal 6 mhz oscillator and can be adjusted by 10 % via control osc_frq, s ee section 7.14 .
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 23 of 93 ? 2017 dialog semiconductor 4.6 backup battery charger unless otherwise noted, the following is valid for t j = - 40 c to + 12 5 oc , v sys = 2.8 v to 5.5 v . table 14 : backup battery charger electrical characteristics parameter symbol test conditions min typ max unit backup battery charging current i set_bchg v sys = 3.6 v v bbat = 2.5 v 100 note 1 6000 a charger termination voltage v set _bchg v sys = 3.6 v 1.1 note 2 3.1 v backup battery short circuit current i s hort v bbat = 0 v 6.5 ma stabilization capacitor c out - 55 % 470 +35 % nf output capacitor esr r c out _esr f > 1 mhz 100 m ? dropout voltage v dropout i out = 5 ma 150 200 mv note 1 can be set in 100 a steps from 100 a to 1000 a and 1 ma steps from 1 ma to 6 ma via bchg_iset in register bbat_cont. note 2 can be set in 100/200 mv steps via bchg_vset in register bbat_cont. 4.7 32 khz crystal oscillator unless ot herwise noted, the following is valid for t j = - 40 c to + 12 5 oc , v sys = 2.8 v to 5.5 v . table 15 : 32 khz crystal oscillator electrical characteristics parameter symbol test conditions min typ max unit supply voltage v ddrtc derived from v bbat or v ddcore 1.5 2.75 v oscillator frequency f osc 32.768 khz clock jitter cycle to cycle 1000 cycles 20 35 ns crystal esr r xtal 50 100 k ? crystal cap c xtal 2 pf start - up time t start v dd rtc = 1.5 v to 2.75 v 0.5 2 s bypass mode input frequency f in - 5% 32 +5% khz input duty cycle dc 40 60 % xtal_in input high voltage v ih rtc_en = 0 1.8 v sys v rtc_en = 1 v bbat < v sys 1.1 rtc_en = 1 v bbat > v sys 0.7 * v bbat v bbat x tal_ out input low voltage v il rtc_en = 0 - 0.3 0.6 v rtc_en = 1 v bbat < v sys 0.4 rtc_en = 1 v bbat > v sys 0.2 * v bbat input slew rate sr 2 pf input capacitance 0.1 v/ns
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 24 of 93 ? 2017 dialog semiconductor 4.8 internal oscillator unless otherwise noted, the following is valid for t j = - 40 c to + 12 5 oc , v sys = 2.8 v to 5.5 v . table 16 : internal oscillator electrical characteristics parameter symbol test conditions min typ max unit oscillator frequency f osc osc_frq = 0000 5.7 6 6.3 mhz note 1 o scillator frequency can be further adjusted by about 10 % , see section 7.14 . 4.9 system supply v oltage supervision unless otherwise noted, the following is valid for t j = - 40 c to + 12 5 oc , v sys = 2.8 v to 5.5 v . table 17 : system supply v oltage supervision electrical characteristics parameter symbol test conditions min typ max unit under - voltage lockout lower threshold v por_lower 2.0 v under - voltage lockout upper threshold v por_upper 2.3 v v sys under - voltage lower threshold v dd_fault_lower note 1 2.5 2.8 3.25 v v sys under - voltage lower threshold accuracy v sys_lower - 2 +2 % v sys hysteresis v dd_fault_h ys note 2 100 200 450 mv v sys upper threshold v dd_fault_upper - 2 % v dd_fault_lower + v dd_fault_hys + 2 % reference voltage v ref - 1% 1.2 +1% v vref decoupling capacitor c vref 2.2 f reference current resistor r iref - 1% 200 +1% k ? note 1 can be set in 50 mv steps via control vdd_fault_adj in register config_b , setting v dd_fault_lower 2.65 v avoids ldocore dropout, see section 4.4.3 . note 2 can be set in 50 mv steps via control vdd_hyst_adj in register config_b.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 25 of 93 ? 2017 dialog semiconductor 4.10 junction t emperature supervision unless otherwise noted, the following is valid for t j = - 40 c to + 12 5 oc , v sys = 2.8 v to 5.5 v . table 18 : junction t emperature supervision electrical characteristics parameter symbol test conditions min typ max unit por temperature threshold note 1 t por note 2 135 150 165 c critical temperature threshold note 1 t crit note 2 125 140 155 c warning temperature threshold note 1 t warn note 2 110 125 140 c note 1 s ee section 7.10 . note 2 thermal thresholds are non - overlapping. 4.11 current consumption unless otherwise noted, the following is valid for t j = - 40 c to + 12 5 oc , v sys = 2.8 v to 5.5 v . table 19 : current consumption electrical characteristics operating mode symbol test conditions vbbat (typ) vsys (typ) unit rtc mode i dd rtc v sys > 2. 0 v v bbat > v sys 1.5 note 1 1.0 a v sys > 2. 0 v v bbat < v sys 0.5 7 note 2 a powerdown mode i dd pd v sys > 3.0 v ldocore enabled bucks and ldos disabled 40 a active mode i dd act bucks and ldos enabled 400 a note 1 maximum current is 2.5 a for t a ? 85 ? c and v bbat ? 3.1 v. note 2 maximum current is 10 a for t a ? 85 ? c and v sys ? 5.0 v.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 26 of 93 ? 2017 dialog semiconductor 5 typical characteristics figure 4 : buck 1 efficiency in auto mode figure 5 : buck 2 efficiency in auto mode
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 27 of 93 ? 2017 dialog semiconductor figure 6 : buck 3 efficiency in auto mode (v in = 3.60 v , v out = 1.80 v) figure 7 : buck3 efficiency in auto mode (v in = 5 . 00 v, v out = 3.34 v)
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 28 of 93 ? 2017 dialog semiconductor figure 8 : buck 4 efficiency in auto mode
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 29 of 93 ? 2017 dialog semiconductor 6 system block diagram a block diagram for a typical application is illustrated in figure 9 . figure 9 : da9062 - a typical system block diagram d a 9 0 6 2 b u c k 2 b u c k 3 b u c k 1 b u c k 4 0 . 8 v t o 3 . 3 v ( 2 a ) v d d q 1 . 5 v ( 2 . 5 a ) v t t 0 . 7 5 v ( 7 0 0 m a ) a p p l i c a t i o n p r o c e s s o r c o i n c e l l d d r 3 m e m o r y 0 . 9 v t o 3 . 6 v ( 1 0 0 m a ) b b a t c h a r g e r r t c 0 . 9 v t o 3 . 6 v ( 3 0 0 m a ) 0 . 9 v t o 3 . 6 v ( 3 0 0 m a ) 0 . 9 v t o 3 . 6 v ( 3 0 0 m a ) 0 . 7 v t o 1 . 5 7 v ( 2 . 5 a ) l d o 1 v s y s l d o 2 v d d _ l d o 2 v d d _ l d o 3 4 l d o c o r e l d o 4 l d o 3 v d d _ b u c k 4 v d d _ b u c k 1 v d d _ b u c k 2 v d d _ b u c k 3 v d d q ( g p i o 0 )
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 30 of 93 ? 2017 dialog semiconductor 6.1 ddr power management using da9062 - a f or ddr power management is illustrated in figure 10 . figure 10 : da9062 - a ddr power management b u c k c o n t r o l b u c k c o n t r o l v b u c k 1 d a c d a c v b u c k 4 v d d _ b u c k 4 v d d _ b u c k 1 v l x _ b u c k 1 v l x _ b u c k 4 v b u c k 1 v d d q ( 2 . 5 a ) v t t ( 7 0 0 m a ) v d d q v t t r ( 1 0 m a ) 5 v b u c k 1 / 2 b u c k 4 v b u c k 4
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 31 of 93 ? 2017 dialog semiconductor 7 functional description 7.1 control signals each of the input signals described below feature a debounce filter. they share a common debounce time control (debouncing). 7.1.1 nonkey nonkey is an edge - sensitive signal that controls the power mode of da9062 - a . both falling and rising edges are detected and the time between the edges is measured. this enables different lengths of key press detection. the detection circuitry is e nabled in all power modes of the device. the status of the signal after debouncing can be read from n onkey (reg ister status_a) . the mask bit m_ n onkey prevents interrupt and wake - up events that would normally be caused by an nonkey event. nonkey has four m odes of operation, see table 20 , which can be selected by n onkey_pin. n onkey_lock controls the wake - up event generation of the nonkey. if n onkey_lock i s asserted (depends on n onkey_pin), a short nonkey press (shorter than key_delay) will not generate a wake - up . table 20 : n onkey functions n onkey_pin function 00 an event (e_nonkey) is generated when nonkey is asserted. if not masked, t he event causes an interrupt. a wake - up is triggered if the device is in powerdown mode. 01 a timer is started when nonkey is asserted. if the signal is de - asserted before the time programmed in key_delay , an event (e_nonkey) is generated at the rising edge. if the signal stays asserted and the timer reaches the programmed value, an event is generated and nonkey_lock is asserted. 10 a timer is started when nonkey is asserted. if the signal is de - asserted before the time programmed in key_delay , an event (e_nonkey) is generated at the rising edge. if the signal stays asserted and the timer reaches the programmed value, an event is generated, nonkey_lock is asserted, and a power - down sequence is triggered by automatically clearing system_en. 11 a timer is started when nonkey is asserted. if the signal is de - asserted before the time programmed in key_delay, an event (e_nonkey) is generated at the rising edge, system_en is cleared, and standby is asserted. if the signal stays asserted and the timer reaches the programmed value, an event is generated, nonkey_lock is asserted, and system_en and standby are cleared. whenever nonkey_lock is asserted, a long key press (longer than the time programmed in key_delay) is required to wake up from powerdown mo de. if the wake up is also desired after a short key press, nonkey_lock has to be cleared before entering the powerdown mode. 7.1.2 nresetreq nresetreq is an active - low reset request that causes da9062 - a to enter reset mode. the transition to the reset mode i s handled by the power sequencer and it can be sped up by setting the host_sd_mode bit. before entering the reset mode, a fault log bit is set (nresetreq) and nreset is asserted. nresetreq should be tied to an always - on rail that is supplied in all modes o f the da9062 - a such as vsys. it is not recommended to tie nresetreq to any of the regulator outputs.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 32 of 93 ? 2017 dialog semiconductor 7.1.3 nreset nreset is an active - low reset output intended for resetting the host processor of the system. the signal can be configured as either push - pull or open drain output (pm_o_type). nreset is always asserted upon a cold boot from the no - power mode. it is always asserted at the beginning of a shutdown sequence to the reset mode. nreset may also be asserted at the beginning of the sequence to the power down mode, if configured in control n res_mode. d e - assertion of nreset is controlled by a reset timer. after being asserted, nreset remains low until the reset timer, which was started from the selected trigger signal, expires. the reset timer trigger can be selected via reset_event and set to one of the following: an external signal triggering the wake up (ext_wakeup), an internal signal indicating the end of the first power - up sub - sequence (sys_up), an internal signal indicating the end of the second powe r - up sub - sequence (pwr_up), or the transition of da9062 - a from reset to powerdown mode. the expiry time can be configured via reset_timer from 1 ms to 1 s. if reset_timer is set to 0 ms, nreset is de - asserted immediately after the trigger selected with r eset_event. 7.1.4 nirq nirq is a level - sensitive interrupt signal. it can be configured either as a push - pull or an open drain output (selected via pm_o_type). the polarity of nirq can be selected with irq_type. nirq is asserted when an unmasked event has occur red. the nirq will not be released until all event registers have been cleared. new events that occur while reading an event register are saved until the event register is cleared, ensuring that the host processor captures them. the same will happen to all events occurring when the power sequencer is in transition. 7.2 2 - wire interface the 2 - wire interface provides access to the control and status registers. the interface supports operations compatible to the standard, fast, fast - plus, and high - speed modes of the i 2 c bus specification rev. 3. communication on the 2 - wire bus is always between two devices; one acting as the master and the other as the slave. the da9062 - a only operates as a slave. scl transmits 2 - wire clock data and sda transmits the bidirectio nal data. the 2 - wire interface is open - drain supporting multiple devices on one line. the bus lines have to be pulled high by an external pull - up resistor (2 k ? to 20 k?). the attached devices drive the bus lines low by connecting them to ground. as a resu lt, two devices can drive the bus simultaneously without conflict. in standard/fast mode the highest frequency of the bus is 400 khz. the exact frequency can be determined by the application and it does not have any relation to the da9062 - a internal cloc k signals. da9062 - a stays within the described host clock speed limitations and does not initiate clock slow - down. an automatic interface reset is triggered when the clock signal ceases toggling for >35 ms (controlled in twowire_to). when the sda is stuc k, the bus clears after receiving nine clock pulses. operation in high - speed mode at 3.4 mhz requires a minimum interface supply voltage of 1.8 v and a mode change in order to enable slope - control. the high - speed mode can be enabled on a transfer - by - transfer basis by sending the master code (0 000 1xxx) at the beginning of the transfer. the da9062 - a does not make use of clock stretching and delivers read data without delay up to 3.4 mhz. alternatively, the interface can be configured to use high - speed mode continuously via pm_if_hsm, so that t he master code is not required at the beginning of every transfer. this reduces communication overhead on the bus and limits the attachable bus slaves to compatible devices.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 33 of 93 ? 2017 dialog semiconductor 7.2.1 register map paging the 2 - wire interface has direct access to two pages of the d a9062 - a register map (up to 256 addresses). the register at address zero on each page is used as a page control register (the lsb of control page is ignored). writing to the page control register changes the active page for all subsequent read/write oper ations unless an automatic return to page 0 is selected using control revert. unless revert was asserted after modifying the active page, it is recommended to read back the page control register to ensure that future data exchange is accessing the intended registers. da9062 - a also offers an alternative way to access register pages which avoids writing explicitly to page. da9062 - a responds to multiple consecutive slave addresses and updates page automatically based on the slave address. for example, when if_base_addr[7:4] = 0xb the slave address changes page as follows: slave address = 0xb0 ? page = 0x00 slave address = 0xb 2 ? page = 0x02 7.2.2 details of the 2 - wire protocol all data is transmitted across the 2 - wire bus in 8 - bit groups. to send a bit, the sda l ine is driven at the intended state while the scl is low. once the sda has settled, the scl line is brought high and then low. this pulse on scl stores the sda bit in the receivers shift register. a 2 - byte serial protocol is used: one address byte and one data byte. data and address transfer transmits the msb first for both read and write operations. all transmissions begin with the start condition from the master during which the bus is in idle state (the bus is free). it is initiated by a high - to - low tra nsition on the sda line while the scl is in high state. a stop condition is indicated by a low - to - high transition on the sda line while the scl is in high state. the start and stop conditions are illustrated in figure 11 . figure 11 : timing of the start and stop conditions da9062 - a monitors the 2 - wire bus for a valid slave address whenever the interface is enabled. it responds immediately when it receives its own slave address. this is acknowledged by pulling the sda line low during the following clock cycle (white blocks marked wit h a in the following figures). the protocol for a register write from master to slave consists of a start condition, a slave address, a read/write - bit, 8 - bit address, 8 - bit data, and a stop condition. da9062 - a responds to all bytes with an ack. a registe r write operation is illustrated in figure 12 . figure 12 : byte write operation s t a r t s t o p s d a s c l t r a n s a c t i o n slaveadr w regadr a data a p s = start condition a = acknowledge ( low) p = stop condition w = write (low) master to slave slave to master 7 - bits 1 - bit 8 - bits 8 - bits a s
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 34 of 93 ? 2017 dialog semiconductor when the host reads register data the da9062 - a first has to access the target register address with write access and then with read access and a repeated start, or alternatively a second start, condition. after receiving the data, the host sends nack and terminates the tran smission with a stop condition, see figure 13 . figure 13 : examples of byte read operations consecut ive (page) read - out mode is initiated from the master by sending an ack instead of nack after receiving a byte, see figure 14 . the 2 - wire control block then increments the address pointer to the next register address and sends the data to the master. the data bytes are read continuously until the master sends a nack followed by a subsequent stop condition directly after receiving the data. if a non - existent 2 - wire address is read out then the da9062 - a will return code zero. figure 14 : 2 - wire page read the slave ad dress after the repeated start condition must be the same as the previous slave address. consecutive (page) write mode is supported if the master sends several data bytes after sending the register address. the 2 - wire control block then increments the address pointer to the next 2 - wire address, stores the received data, and sends an ack until the master sends a stop condition. the page write mode is illustrated in figure 15 . figure 15 : 2 - w ire page write s slaveadr w a regadr a slaveadr a s = start condition a = acknowledge ( low) sr = repeated start condition a * = no a cknowledge p = stop condition w = write (low) r = read (high) master to slave 7 - bits 1 - bit 8 - bits 7 - bits data a * sr r 1 - bit 8 - bits slaveadr a 7 - bits data p s r 1 - bit 8 - bits p a * slave to master s slaveadr w a regadr p 7 - bits 1 - bit 8 - bits a s slaveadr w a regadr a slaveadr a s = start condition a = acknowledge (low) sr = repeat start condition a * = no acknowledge p = stop condition w = write (low) r = read (high) master to slave slave to master 7 - bits 1 bit 8 - bits 7 - bits data a sr r 1 - bit 8 - bits s slav eadr w a regadr a slaveadr a 7 - bits 1 - bit 8 - bits 7 - bits data p s r 1 - bit 8 - bits p a a * p data data a a * data 8 - bits 8 - bits 8 - bits s sla veadr w a regadr a data a s = start condition a = acknowledge (low) sr = repeat start condition a * = no acknowledge p = stop condition w = write (low) r = read (high) master to slave slave to master 7 - bits 1 bit 8 - bits 8 - bits data a 1 - bit 8 - bits a p data . a 8 - bits repeated writes
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 35 of 93 ? 2017 dialog semiconductor a repeated write mode can be enabled with write_mode control. in this mode, the master can execute back - to - back write operations to non - consecutive addresses by transmitting register addresses and data pairs. the data is stored in the addr ess specified by the preceding byte. the repeated write mode is illustrated in figure 16 . figure 16 : 2 - wire repeated write if a new start or stop condition occurs within a message, the bus returns to idle mode. 7.3 gpios da9062 - a features five general purpose io pins. the basic structure of the gpios is depicted in figure 17 . as illustrated, there are several additional functions: analog function alternate function forwarding regulator control sequencer wait_step interrupt and wake up generation the gpios are operational in powerdown and active modes. however, gpis can be configured as disabled in powerdown mode in register pd _dis (control gpi_dis) . in other modes, the gpio is disabled and all ports are configured as open drain outputs in high impedan ce state. the level transitions on inputs will no longer be detected, but i/o drivers will keep their configuration and programmed levels. figure 17 : general gpio block diagram the functionality of a gpio is configured in gpio < x > _pin, as listed in table 21 . s sla veadr w a regadr a data a s = start condition a = acknowledge (low) sr = repeat start condition a * = no acknowledge p = stop condition w = write (low) r = read (high) master to slave slave to master 7 - bits 1 bit 8 - bits 8 - bits regadr a 1 - bit 8 - bits a p data . a 8 - bits repeated writes g p i o x _ p u p d d e b o u n c e g p i x g p i o x _ m o d e e d g e d e t e c t i o n g p i o x _ t y p e e _ g p i o x m a s k m _ g p i o x g p i o x _ m o d e g p i o x _ p u p d v d d i o w a k e u p s e l e c t i o n v d d i o i n t e r r u p t w a k e u p o u t p u t f u n c t i o n g p i o x _ o u t a l t e r n a t e f u n c t i o n g p i o x _ p i n g p o o d g p o p u s h - p u l l g p i f o r w a r d i n g i n p u t f o r w a r d i n g o u t p u t g p i o x _ w k u p _ m o d e s e q u e n c e r ( w a i t _ s t e p ) , r e g u l a t o r c o n t r o l w a k e u p e n a b l e g p i o x _ w e n s e q u e n c e r c l k _ 3 2 k v d d _ f a u l t 0 1 a n a l o g f u n c t i o n g p i o x _ p i n
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 36 of 93 ? 2017 dialog semiconductor table 21 : gpio functions gpio < x > _ pin function gpio < x > _mod e gpio < x > _ty pe gpio < x > _wkup_mo de gpio < x > _wen 0 alternate function no e ffect no e ffect no e ffect no e ffect 1 gpi 0: debounce off 1: debounce on 0: active low 1: active high 0: edge - sensitive wake up 1: level - sensitive wake up 0: wake up disabled 1: wake up enabled 2 gpo open drain 0: output low 1: output high no e ffect no e ffect no e ffect 3 gpo push - pull 0: output low 1: output high no e ffect no e ffect no e ffect 7.3.1 gpi functionality in gpi mode, the polarity of the input can be selected with gpio < x > _type. a debouncing filter can be applied on the input signals with a configurable debouncing time ( control debouncing). an event is generated at the active edge of the input. the active edge is determined by the signal polarity configured in gpio < x > _type. the even t can be further configured to generate a wake - up via gpio < x > _wkup_mode and gpio < x > _wen. an internal pull - down can be activated for the inputs in gpio < x > _pupd. a level sensitive wake - up event can also be configured for each gpi via gpio < x > _wkup_mode and g pio < x > _wen. the functionality of the level - sensitive wake up is described in table 26 . 7.3.1.1 regulator control gpio1, gpio2, and gpio3 can be used for controlling da9062 - a regulators. when configured as gpis, they can be used to enable regulators or select between their two output voltage settings. as seen in figure 17 , the regulator control is branched after the gpio < x > _type control allowing active edge delegation for the regul ator control. finally, the functionality for the gpi is selected with the regulator control s buck < x > _gpi, ldo < x > _gpi, vbuck < x > _gpi, and vldo < x > _gpi. one gpi can be used to control the same function on multiple regulators simultaneously. when a regulator i s controlled by a gpi, the same function (on/off or voltage selection) can no longer be controlled by the power supply sequencer. the regulator still responds normally to register writes to the control bit. enable/disable control a gpi is used for enabling/disabling regulators when it is selected in one of the buck < x > _gpi or ldo < x > _gpi controls . a passive to active transition sets the regulator enable bit (buck < x > _en, ldo < x > _e n ), and an active to passive transition clears it. output voltage control a gpi is used for the output voltage selection when it is selected in one of the vbuck < x > _gpi or vldo < x > _gpi controls . a passive to active transition set s the voltage selection bit (vbuck < x > _sel, vldo < x > _sel), and an active to passive edge clear s it. 7.3.1.2 sequencer wait_step gpio3 can be used for the wait_step functionality. the power sequencer can be programmed to wait for either a rising or falling edge of the wait_step input , see s ection 7.9.4 . the active edge is selected from gpio < x > _type.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 37 of 93 ? 2017 dialog semiconductor 7.3.2 gpo functionality the outputs can be configured as push - pull or open drain outputs , see table 21 . an internal pull - up can be enabled/disabled from gpio < x > _pupd (open drain mode). the gpio < x > _mode settings can control the output state. instead of controlling the output with gpio < x > _mode, a selection of alternat ives is available in the gpio < x > _out controls . these include: the forwarding function , see s ection 7.3.4 , the power supply sequencer , see se ction 7.9 , the 32 khz clock (out_32k) , and the status of the supply voltage supervision ( n vdd_fault). when the gpio is configured as an output and gpio < x > _out is set to 0x0, the gpio < x > _mode determines the state of the output . 7.3.2.1 nvdd_fault nvdd_fault gives the status of the system supply monitoring , see s ection 7.11 . the assertion of nvdd_fault indicates that the main supply input voltage is low (v sys < v dd_fault_upper ) and therefore informs the h ost processor that the power will soon shut down. it can be configured to drive a gpo from the gpio < x > _out controls . the driver type (push - pull, open drain) selection and pull - up resistor control function normally. the gpio < x > _mode can be used to invert the incoming n vdd_fault signal. 7.3.2.2 out_32k out_32k feeds a buffered 32 khz clock signal that is derived from the internal oscillator. the signal output buffer can be controlled either with the power sequencer or manually via en_32k out, and paused automatically during powerdown mode with the out_32k_pause bit. glitch - free switching between a 32 khz clock output and another gpio configuration is not guaranteed. therefore, configuring a gpio for 32 khz clock output should only be done in otp. however, enabling and disabling the buffer is still dynamic as described above. 7.3.3 alternate functions gpio0, gpio2, and gpio4 can be used for alternate functions. these are digital control signals that dont employ the debouncing, event detection, o r interrupt generation functions. only the input buffer of the gpio block is employed. the alternate functions of da9062 - a are listed in table 22 and described in the following subsections. a debouncing filter can be applied also on the alternate functions with a configurable debouncing time ( control debouncing). table 22 : gpio alternate input functions gpio alternate function d escription gpio0 wdkick watchdog kick or disable gpio1 - gpio2 pwr_en power mode control gpio3 - gpio4 sys_en power mode control 7.3.3.1 sys_en sys_en (pin gpio4) controls the system_en bit and thereby the power mode of da9062 - a . it is part of the power supply sequencer functionality described in s ection 7.9 . sys_en is an edge - sensitive signal and its polarity can be chosen in the gpio4_type control . asserting sys_en causes an interrupt (e_gpix) and a wake - up event. de - asserting sys_en triggers a power - down sequence but no interrupt .
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 38 of 93 ? 2017 dialog semiconductor 7.3.3.2 pwr_en pwr_en (pin gpio2) controls the power_en bit and thereby the power mode of da9062 - a . it is part of the power supply sequencer functionality described in s ection 7.9 . pwr_en is an edge - sensitive signal and its polarity can be chosen in the gpio2_type control . a wake - up event can be generated after assertion of pwr_en if so configured in gpio2_wen. 7.3.3.3 wd kick a rising edge of the wdkick signal resets the watchdog counter. the polarity of the signal can be chosen in the gpio0_type control . if the signal is kept asserted, the watchdog is disabled as the counter is not incremented (wdg_mode) , see section 7.15 . 7.3.4 gpio forwarding gpio forwarding works between gpios 0, 1, 2, and 3. any of these gpis can be routed directly to gpo 0, 1, and 3 after debouncing. forwarding is one of the options for the gpio < x > _out control. 7.3.5 analog functions gpio0 and gpio1 can be used as analog ios. in this case, the normal gpio functions are disabled. the analog functions and their corresponding control bits ar e listed in table 23 . table 23 : gpio analog functions gpio analog function control gpio0 vddq buck 4 _vtt_en gpio1 vttr buck 4 _vttr_en gpio2 - gpio3 - gpio4 - 7.4 dynamic voltage control all of da9062 - a s buck converters can be controlled in several ways to achieve dynamic voltage control (dvc). the buck converters feature a voltage ramping feature that enables smooth transition from one voltage setting to another. all output voltages can be controlled with software via the 2 - wire interface (vbuck < x > _a). the 2 - wire interface is operational when the device is in active mode. 7.5 regulator voltage a and b selection in addition, all regulators feature a and b settings which can be programmed with different voltages (vbuck < x > _a, vbuck < x > _b), one of which is chosen according to the operating mode of the system (vbuck < x > _sel, vldo < x > _sel). in addition to the output voltage, the a and b settings include a bit to force the regulator into sleep mode which reduces the quiescent current. the selection between the a and b setting s can be done either with software via t he 2 - wire interface or by the power sequencer , see s ection 7.9 . furthermore, each regulator can be enabled with a gpi pin , see s ection 7.3.1.1 , and the selection between the a and b settings done with another gpi.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 39 of 93 ? 2017 dialog semiconductor 7.6 ldos all ldos employ dialog semiconductors smart mirror? dynamic biasing techno logy , see figure 18 , which maintains high performance over a wide range of operating conditions and a power saving mode (sleep mode) to minim ize the quiescent current during very low output current. the circuit technique offers significantly higher gain bandwidth performance than conventional designs, enabling higher power supply rejection performance at higher frequencies. psrr is maintained across the full operating current range however quiescent current consu mption is scaled to demand improved efficiency when current demand is low. figure 18 : smart mirror voltage regulator 7.6.1 control the ldos can be enabled by writing directly to a control bit (ldo < x > _en), controlling it via a gpi , see s ection 7.3.1.1 , or assigning it to a power sequencer step , see s ection 7.9.2 . each ldo features two voltage control registers (vldo < x > _a/vldo < x > _b) that allow two output voltage pre - configurations. the active setting can then be selected either with a control bit (vldo < x > _sel) , via a gpi , see s ection 7.3.1.1 , or automatically based on the da9062 - a power mode. the sleep mode of the ldos can be linked to either the a or b setting (ldo < x > _sl_a/ldo < x > _sl_b). therefore, the ldo will switch to sleep mode when the setting is active. ldo1 differs from the other ldos because it can be configured as an always - on regulator. this means that it is also enabled in reset mode, see section 7.8.3 . 7.6.2 current limit each ldo provides over - current detection. the current limit is fixed for each ldo based on their current capability. if any of the ldos current limit is exceeded for longer than 10 ms, an event, e_ldo_lim, is triggered. the status of the limit comparator can be observed from ldo < x > _ilim ( register status_d) . if an ldos current limit is exceeded for longer than 200 ms, the ldo is automatica lly disabled. this shutdown feature can be disabled by clearing the ldo_sd control . once disabled due to an over - current, the ldo must be re - enabled by one of the sources described in s ection 7.6.1 . 7.6.3 output pull - down when over - voltage (1.06 * vldo < x > ) occurs, the voltage regulators enable an internal load to discharge the output back to its configured voltage. this feature can be disabled in ldo < x > _p d_dis. v o u t c o u t e s r v i n s m a r t m i r r o r t m l d o v r e f
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 40 of 93 ? 2017 dialog semiconductor 7.7 switching regulators da9062 - a includes four step - down switching regulators operating at 3 mhz. all switching regulators employ a synchronous topology with an internal nfet, thus eliminating the need for an external schottky diode. the output vol tage can be set in 10 mv steps (20 mv steps for buck3) and the regulation accuracy is 3 % over the whole operating temperature range. static line and load regulation are also considered in this accuracy. the switching frequency (3 mhz) is high enough to warrant the use of a small 1.0 h inductor. the programming of the converter current limit depends on the coil parameters, as illustrated in table 24 . table 24 : buck current limit min. isat (ma) frequency (mhz) buck current limit (ma) 1750 3 1500 1460 3 1200 1180 3 950 940 3 750 7.7.1 control the buck can be enabled manually by writing directly to a control register, with an external signal connected to gpi , see s ection 7.3.1.1 , or by assigning it to a power sequencer step , see s ection 7.9.2 . each buck converter features two voltage control registers (vbuck < x > _a/vbuck < x > _b) which can be pr ogrammed with two different voltages. the active setting can then be selected via a control bit (vbuck < x > _sel), via a gpi , see s ection 7.3.1.1 , or automatically based on the power mode of da9062 - a . 7.7.2 output voltage slewing to limit in - rush current from the input supply, the buck converters can achieve a new output voltage with cont rolled ramping. ramping is achieved by stepping through all the v buck values between the old and new settings, at a rate defined by slew_rate. the actual output slew rate, in mv/ s, for a particular buck converter is then defined by the minimum voltage ste p of that buck and the common step time programmed in slew_rate. during pfm mode , the negative slew rate is load dependent and might be lower than the one mentioned above. an event e_dvc_rdy is triggered when all buck converters have reached their target v oltage. 7.7.3 soft - start the buck converter supports two options for starting up. the normal start - up option ramps up the power rail as fast as possible, typically within 1 ms. this implies a high in - rush current. the slow start - up is selected by setting buck_s lowstart, which increases the start - up time and limits the input current. 7.7.4 active discharge when switching off a buck converter the output rail can be actively discharged. this feature is enabled by setting buck_actv_dischrg. the discharge is implemented b y ramping down the output voltage using dvc. 7.7.5 peak current limit all buck converters feature a programmable current limit (buck < x > _ilim). the current limit protects the inductor and the pass devices from excessive current. if the current limit is exceeded, the buck continues to run normally but the duty cycle is limited.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 41 of 93 ? 2017 dialog semiconductor 7.7.6 operating mode the operating mode of each converter can be set via the buck control (buck < x > _mode) to synchronous (pwm), sleep (pfm), or auto. in auto mode the buck converter switches betwe en pwm and pfm depending on the load current. this mode is recommended for applications that require fast transitions from synchronous to sleep operation. the current consumption during pwm operation is 10 ma and drops to <1 a in shutdown. in addition, t he buck mode can be controlled with the a and b setting. if buck < x > _sl_b is set, the buck is forced to sleep mode when the b setting is active. similarly, if buck < x > _sl_a is set, the buck is forced to sleep mode when the a setting is active. 7.7.7 half - current mode buck1 and buck2 can operate in half - current mode where the quiescent current is reduced by disabling half of the pass devices. as the name implies, enabling this option halves the output current, and therefore, this feature is valuable in applications where quiescent current is critical and full current is not needed. this feature is controlled with buck1_fcm and buck2_fcm. if the bit is asserted (buck < x > _fcm = 1), the corresponding buck is in full - current mode and the full current is available. if the bit is de - asserted , the corresponding buck is in half - current mode. operating the buck s in full - current mode requires twice as much output capacit ance (2 x 47 f) as the half - current mode (2 x 22 f). 7.7.8 buck1 and buck2 in dual - phase mode b uck 1 and buck 2 can be merged as a dual - phase buck, with up to 5 a output current. if enabled in otp via b uck1_2_ merg e, the output s from both inductors must be routed together . the controls for buck 2 are automatically disabled in this configuration, except for b uck2 _pd_dis. 7.7.9 buck4 in ddr memory bus termination mode buck4 can be used to generate the ddr memory termination voltage , vtt. in this mode, buck4 tracks the divided vddq voltage and it is able to both sink and source current. as described in s ection 7.3.5 , gpio0 can be configured to carry the vddq and gpio1 can be configured to carry the vttr signal. the vttr output provides buffered version of the vddq/2 voltage with 10 ma source/sink capability (requires 0.1 f stabilization capacitor) , see figure 19 . when used for memory termination, buck 4 has to be forced in the synchronous (pwm) mode from the buck4_mode control . if buck4_vtt_en and buck4 _vtt r _en are asserted at the same time , the vttr provides a buffered vtt reference , but otherwise buck4 is running in a normal output voltage control mod e. figure 19 : buck4 ddr memory bus termination mode b u c k 4 b u c k c o n t r o l d a c v b u c k 4 v l x _ b u c k 4 v t t ( 7 0 0 m a ) v d d q g p i o 0 v t t r ( 1 0 m a ) g p i o 1 v b u c k 4 v d d _ b u c k 4 b u c k 4 _ v t t _ e n + -
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 42 of 93 ? 2017 dialog semiconductor table 25 : buck4 vtt mode control b uck 4_v tt _e n b uck 4_v ttr _e n mode buck4 v ref gpio0 gpio1 0 0 normal vdac digital i/o digital i/o 0 1 normal vdac vddq vttr 1 0 vtt vddq/2 un - buffered vddq digital i/o 1 1 vtt vddq/2 buffered vddq vttr 7.8 power modes figure 20 : da9062 - a power modes (state transition conditions follow c - language syntax) n o - p o w e r r t c a c t i v e f u n c t i o n s v d d c o r e c o m p a r a t o r 3 2 k h z o s c i l l a t o r r t c c o u n t e r n o n k e y a c t i v e f u n c t i o n s v d d c o r e c o m p a r a t o r p o w e r d o w n a c t i v e r e s e t a c t i v e f u n c t i o n s v d d c o r e c o m p a r a t o r 3 2 k h z o s c i l l a t o r r t c c o u n t e r n o n k e y i n t e r n a l s u p p l i e s l d o 1 a c t i v e f u n c t i o n s v d d c o r e c o m p a r a t o r 3 2 k h z o s c i l l a t o r r t c c o u n t e r n o n k e y i n t e r n a l s u p p l i e s l d o 1 s e l e c t e d s u p p l i e s a c t i v e f u n c t i o n s v d d c o r e c o m p a r a t o r 3 2 k h z o s c i l l a t o r r t c c o u n t e r n o n k e y i n t e r n a l s u p p l i e s a l l s u p p l i e s w a t c h d o g v d d c o r e > v p o r _ u p p e r ( n o n k e y p r e s s | | r t c a l a r m ) & & ( ! t e m p e r r o r & & ! v s y s e r r o r ) n o n k e y p r e s s | | g p i o w a k e - u p e v e n t n r e s e t r e q | | n o n k e y ( l o n g ) n o n k e y ( s h o r t ) | | g p i o p o w e r - d o w n e v e n t | | w a t c h d o g t i m e o u t n r e s e t a s s e r t e d t i m e > r e s e t _ d u r a t i o n & & ( ! t e m p e r r o r & & ! v s y s e r r o r ) n r e s e t r e q | | n o n k e y ( l o n g ) r t c _ m o d e _ p d v s y s e r r o r v d d c o r e < v p o r _ u p p e r a n y s t a t e p o w e r d o w n ( f r e e z e ) r e t r y c o u n t = = 0 a n y s t a t e t e m p e r r o r r e t r y c o u n t ! = 0 p o w e r - u p s e q u e n c e n r e s e t r e q | | n o n k e y ( l o n g ) p o w e r - d o w n s e q u e n c e s h u t d o w n s e q u e n c e s h u t d o w n s e q u e n c e s h u t d o w n s e q u e n c e a n y s t a t e r t c _ m o d e _ s d s e q u e n c e d o n e | | t i m e o u t s e q u e n c e d o n e | | t i m e o u t s e q u e n c e d o n e | | t i m e o u t s e q u e n c e d o n e | | t i m e o u t w a t c h d o g a l i v e
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 43 of 93 ? 2017 dialog semiconductor 7.8.1 no - power mode the no - power mode is initial state when powering up the da9062 - a for the first time. when the system supply rises above a threshold, da9062 - a enters reset mode. 7.8.2 rtc mode the rtc mode is a low - power mode with only a minimum set of functions to maintain the system time. all supplies are disabled. rtc mode is entered either after a software request or when the backup battery is the only supply. if enabled in control rtc_mode _pd, the power sequencer proceeds automatically from the powerdown state to rtc mode. if the system supply is removed, da9062 - a will also enter rtc mode. supply recovery will trigger an exit from rtc mode automatically. da9062 - a will exit rtc mode when nonkey is asserted, or an rtc alarm is raised. gpios are not operational in rtc mode. 7.8.3 reset mode in reset mode, the internal supplies, and ldo1 (if configured as an always - on supply ) are enabled. all other da9062 - a supplies are disabled. da9062 - a is in reset mode whenever a complete application shutdown is required. reset mode can be triggered by the user, a host processor, or an internal event. reset mode can be triggered by the user: from a long press of nonkey (interruptible by host) defined by control shut_delay. by pressing a reset switch that is connected to port nresetreq (non - interruptible) reset mode can be forced from the host processor (non - interruptible): by asserting nresetreq (falling edge) by writing to control shutdown da 9062 - a error conditions that force reset mode (non - interruptible) are : no watchdog write (wdkick signal assertion) from the host inside the watchdog time window (if watchdog was enabled) an under - voltage detected on v sys (v sys < v dd_fault_lower ) an inter nal junction over - temperature with the int_sd_mode, host_sd_mode and key_sd_mode controls, the shutdown sequences from internal fault, host or user triggered, are individually configured to either implement the reverse timing of the power - up sequence or tr ansfer immediately to the reset mode by skipping any delay from sequencer or dummy slot timers. for the host to determine the reason for the reset a fault_log register stores the root cause (either key_reset or nresetreq ). the host processor resets this re gister by writing asserted bits with 1. key_sd_mode = 1 triggers a complete power on reset (por) (instead of entering reset mode) after the related keys are pressed extendedly. if an otp read is aborted, da9062 - a enters reset mode without an asserted b it inside register fault_log. a shutdown sequence to reset mode will start with the assertion of the nreset port. after the sequencer completes the power - down sequence (sequencer position 0), da9062 - a continues to reset mode with only the following activ e circuits: ldocore (at reduced output voltage 2.2 v), control interfaces and gpios, bcd counter, band - gap and over - temperature/vsys comparators. all regulators, except for ldo1 and the backup battery charger, are automatically disabled to avoid battery dr ainage. as described in s ection 7.1.3 , nreset is always asserted at the beginning of a shutdown sequence to reset mode, and remains asserted when da9062 - a is in reset mode. when entering reset mode , all user and system events are cleared . t he da9062 - a s register configuration will be re - loaded from otp when leaving the reset mode (with the exception of control auto_boot in case of a vdd_start f ault).
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 44 of 93 ? 2017 dialog semiconductor fault_log, gp_id_10 to gp_id_19 and other non - otp loaded registers, for example the rtc calendar and alarm, will not be changed when leaving the reset mode. some reset conditions such as writing a 1 to control shutdown , a watchdog error, or a junct ion over - temperature will be automatically cleared . other reset triggers, such as asserting nresetreq, need to be released to proceed from reset to powerdown mode. i f the application requires regulators to discharge completely before a power - up sequence, a minimum duration of the reset mode can be selected via reset_duration. if the reset was initiated by a users long press of nonkey, initially only key_reset is set and the nirq port will be asserted. key_reset signals the host that a shutdown sequence is started. if the host does not then clear key_reset within 1 second by writing a 1 to the related bit in register fault_log, the shutdown sequence will complete. when the reset condition has disappeared, da9062 - a requires a supply (v sys > v dd_fault_upper ) that provides enough power to start - up from the powerdown mode. reset mode also allows automatic transition to rtc mode where all features of da9062 - a , except the rtc oscillator and calendar (including ldocore), are disabled. this mode is selected in control rtc_mode_sd. 7.8.4 powerdown mode the powerdown mode is a low - power state where most of the regulators are disabled. the transition from active to powerdown mode (and vice versa) is handled by the programmable sequencer. entry to powerdown mode from act ive mode is triggered by the de - assertion of system_en (either via sys_en or register access) or by a short press of nonkey. the powerdown mode is also passed during start - up and shutdown to reset mode sequences. in powerdown mode the internal supplies ar e enabled, and the control interface and gpios are operational. the power state machine features a retry counter that limits the number of transitions from powerdown to active under certain conditions. a watchdog timeout triggers powerdown mode entry, but it does not necessarily clear the conditions that trigger a transition back to the active mode. this could cause an endless loop between the active and powerdown modes. therefore, after each watchdog timeout the retry counter is decremented, and after the retry counter reaches zero, da9062 - a blocks all wake - up events and stays in powerdown mode. this freeze function can be regarded as a substate of the powerdown mode that is undetectable from outside the da9062 - a . table 26 describes the state transitions with a level - sensitive wake up and the freeze function. table 26 : state transitions with a level - sensitive gpi current state ls gpi sys _ en pwr _ en freeze note 1 next state powerdown x x x 1 powerdown powerdown 0 0 x 0 powerdown powerdown x 1 0 0 system powerdown x 1 1 0 active powerdown 1 x 0 0 system powerdown 1 x 1 0 active system 0 0 x x powerdown system x 1 0 x system system x 1 1 x active system 1 x 0 x system system 1 x 1 x active
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 45 of 93 ? 2017 dialog semiconductor current state ls gpi sys _ en pwr _ en freeze note 1 next state active 0 0 x x powerdown active x 1 0 x system active x 1 1 x active active 1 x 0 x system active 1 x 1 x active note 1 in this table, freeze represents the result of the comparison retry count = 0 . the following events will reset the retry counter and release the state machine from the freeze state: de - assertion of all blocked level - sensitive wake - up conditions entry to the reset mode ( over - temperature error, nresetreq or long press of nonkey) entry to the rtc mode (system supply error) the freeze operation is illustrated in figure 21 . once the freeze state is cleared, da9062 - a continues operating normally. the freeze function can be enabled in the freeze_en register and the number of retries triggering the freeze can be configured in nfreeze. figure 21 : freeze function 7.8.5 power - up, power - down, and shutdown sequences the power - up, power - down, and shutdown sequences , see figure 20 , are handled by the power supply sequencer, see s ection 7.9 . all power - up sequences are identical, and the power - down sequences mirror the power - up sequences. the shutdown sequences are also identical to the power - down sequence, but after reaching powerdown mode, the state machine automatically proceeds to reset mode. the shutdown sequences caused by an internal error or nresetreq can be sped up from the int_sd_mode and host_sd_mode controls: see s ection 7.8.3 . 7.8.6 active mode in the active mode, all supplies and functions are active. the transition from powerdown to active mode is handled by the programmable sequencer. da9062 - a enters active mode after the sequence has completed and the watchdog is enabled (if configured to use watchdog) . status information can be read from the host processor via the 2 - wire interface and da9062 - a can flag interrupt requests to the host via a dedicated interrupt port (n irq). p o w e r m o d e a c t i v e p o w e r d o w n a c t i v e t w d _ e r r o r g p i 1 n f r e e z e t h e w a t c h d o g e x p i r e s t h e l e v e l s e n s i t i v e w a k e - u p c o n d i t i o n i s b l o c k e d t h e l e v e l s e n s i t i v e w a k e - u p c o n d i t i o n i s d e - a s s e r t e d w h i c h r e s e t s t h e r e t r y c o u n t t h e r e t r y c o u n t i s d e c r e m e n t e d a n d r e a c h e s z e r o t h e s y s t e m o p e r a t e s n o r m a l l y u p o n t h e n e x t w a k e - u p e v e n t r e t r y c o u n t 0
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 46 of 93 ? 2017 dialog semiconductor 7.9 power supply sequencer da9062 - a features a p rogrammable p ower supply s equencer that handles the system power - up, power - down, and shutdown sequences. the sequencer has a step - up counter, a timer that controls the step period, and a set of comparators that trigger power - on/off events at specific steps of the counter. the structure of t he sequencer is depicted in figure 22 . the sequencer is composed of 16 steps, and the step time can be programmed between 32 s and 8.192 ms. the seque ncer will step until it reaches a programmable maximum value (max_count), whereupon an interrupt is issued. at each step, the sequencer will enable all the functions that are pointing to that particular step. the power - up and - down sequences cannot be conf igured separately. when da9062 - a is powering down, the sequencer will execute whatever was configured for the power - up sequence but in reverse order. supplies can also be configured to stay on in powerdown mode. in this case, the sequencer does not disab le the regulator but switches to its b - configuration , see s ection 7.5 . if any pointer is programmed to a step higher than max_count, the function i s no longer controlled by the sequencer. only the regulator control pointers (ldo < x > _step, buck < x > _step) are allowed to point to step 0. setting any other pointer to step 0, effectively disables that function. figure 22 : structure of the power supply sequencer note standby mode can only be reached on power - down, not power - up. p o w e r d o w n m o d e 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 l d o 1 l d o 2 l d o 3 l d o 4 b u c k 1 b u c k 2 b u c k 3 w a i t _ s t e p g p x _ r i s e g p x _ f a l l s y s t e m s y s t e m _ e n d p o w e r _ e n w a k e - u p p o w e r _ e n d p o w e r 1 _ e n m a x _ c o u n t a c t i v e m o d e s y s t e m _ e n w a t c h d o g a l i v e p o w e r p o w e r 1 p d _ d i s _ s t e p o t p _ r d 2 s t a n d b y m o d e p a r t _ d o w n o t p r e a d _ e n b u c k 4
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 47 of 93 ? 2017 dialog semiconductor 7.9.1 sub - sequences as illustrated in figure 22 , the sequencer is partitioned into three sub - sequences. these three sub - sequences can be used to define three power modes for the target application and to move between them in a controlled s equence as a response to control signals or register writes. the first sub - sequence starts from step 0 and ends at a step defined by the system_end pointer. after the power - up is triggered, da9062 - a performs a partial otp read (otp_rd2) if otpread_en is set. it then waits for control system_en to trigger the first sub - sequence. if system_en is already set in the otp the first sub - sequence starts automatically after the power - up trigger. alternatively, system_en can be asserted through the sys_en input. w hen the sequencer reaches the system_end step the first sub - sequence is completed and the sequencer starts waiting for control power_en to trigger the second sub - sequence. if power_en is already set in the otp, the sequencer does not stop after the first s ub - sequence. alternatively, power_en can be asserted through the pwr_en input or via a register access. the second sub - sequence starts from the step following system_end and stops at a step defined by the power_end pointer. when the sequencer reaches the power_end step (and the watchdog is active) , da9062 - a enters active mode. the final sub - sequence is triggered by asserting power1_en via a register write. the third sub - sequence starts from the step following power_end and stops at a step defined by the max_count pointer. if max_count points to an earlier step than system_en d or power_end the remaining steps of the sequencer are disabled. the power - down sequences are executed in reverse order to the power - up sequences. if the power - down sequence is triggered from the active mode by de - asserting power_en, the sequencer stops after reversing to the system_end step. however, if the power - down sequence is triggered by de - asserting system_en, the sequencer does not stop and reverses back to step 0. furthe rmore, if the power - down sequence is triggered by a watchdog timeout, the sequencer reverses to step 0 immediately. a partial power - down can be achieved by setting control standby. this makes the sequencer stop at the step pointed to by the part_down point er. the next power - up will then start from the part_down step, instead of step 0. the part_down pointer has to point to a step smaller than the system_end pointer. 7.9.2 regulator control each of da9062 - a s buck converters and ldos can be assigned to any of th e sequencer steps. in general, when the sequencer reaches a step to which a regulator is assigned, that regulator is enabled by the sequencer. likewise, when the sequencer reaches the same step on the way down, the regulator is disabled. multiple supplies can point to the same counter step; however, enabling multiple regulators in the same slot can lead to increased in - rush currents. in the simplest scheme, the sequencer enables regulators during a power - up, and disables them during a power - down. this func tionality is achieved by setting buck < x > _auto/ldo < x > _auto and clearing buck < x > _conf/ldo < x > _conf. alternatively, the sequencer can be configured to keep the regulator enabled, but switch between the a and b settings in active and powerdown modes. the functi onality of the buck < x > _auto/ldo < x > _auto and buck < x > _conf/ldo < x > _conf controls is summar ize d in table 27 .
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 48 of 93 ? 2017 dialog semiconductor table 27 : regulator control functionality of the power supply sequencer power - up (sequencer direction up) auto conf powerdown mode (before) active mode (after) en sel en sel sequencer functionality 0 0 x x 0 0 the regulator is disabled at the step pointed to by buck < x > _step/ldo < x > _step and the a - setting (vbuck < x > _a/vldo < x > _a) is activated. x 1 x x 1 0 the regulator is enabled at the step pointed to by buck < x > _step/l d o < x > _step and the a - setting (vbuck < x > _a/vldo < x > _a) is activated. 1 x x x 1 0 power - down (sequencer direction down) auto conf active mode (before) powerdown mode (after) en sel en sel x 0 x x 0 0 the regulator is disabled at the step pointed to by buck < x > _step/ldo < x > _step and the a - setting (vbuck < x > _a/vldo < x > _a) is activated. x 1 x x 1 1 the regulator stays enabled but it is switched to the b - setting (vbuck < x > _b/vldo < x > _b). step 0 of the sequencer has a special meaning. if control def_suppl y is set, the sequencer treats all regulators pointing to step 0 as default supplies. this means that th e regulators are enabled automatically when entering the powerdown mode. regulators assigned to other steps are only enabled after a wake - up condition occurs. apart from this, step 0 acts the same as steps 1 to 15. if control def_supply is 0, step 0 of the sequencer does not have any affect. as mentioned in section 7.6.1 , ldo1 can be programmed as an always - on supply. this is achieved by setting contr ols def_supply, ldo1_conf, and ldo1_en in the otp. in normal operation, when the sequencer moves between active and powerdown modes, ldo1 behaves as presented in table 27 . however, if da9062 - a moves to the reset mode, this configuration keeps ldo1 enabled. this is not the case for any other regulator. 7.9.3 gpo control any gpo can be asserted or de - asserted in a sequencer step (gp_rise < x > _step, gp_fall < x > _step). the gpo control is summar ize d in table 28 . if a gpo is controlled by the sequencer , it is driven to its inactive state when da9062 - a is in re set mode. the gpio control only works in sequencer steps greater than zero. table 28 : gpo control functionality of the power supply sequencer gpio _mode gpo state after reset sequencer direction previous gpo state gpo transition at gp_rise gpo transition at gp_fall 0 (active low) high up high high to low - low - low to high down high - high to low low low to high - 1 (active high) low up high - high to low low low to high - down high high to low - low - low to high
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 49 of 93 ? 2017 dialog semiconductor 7.9.4 wait step one of the sequencer steps (any step greater than zero) can be configured as a wait step, in which the sequencer stays until an event is detected in the gpi3 input , see s ection 7.3.1.2 . note t he e_gpi3 event has to be cleared after the power - up sequence completes. otherwise, the wait step in the next power - up sequence will be ineffective. the wait step features an optional 500 ms timeout , which can be used when the wait event never occurs. if the timeout occurs, the steps following the wait step are not executed and a shutdown sequence to reset mode is triggered. the shutdown reason is sign aled with the wait_shut bit. alternatively, the wait step can be used as a configurable delay in the sequence (wait_mode, wait_time). 7.9.5 32 kh z clock output if a gpo is used as a 32 khz clock output see s ection 7.3.2.2 , the clock buffer can be enabled/disabled in one of the sequencer steps (any step greater than zero). the clock buffer is enabled when, during power - up, the sequencer reaches the step en3 2k_step. likewise, the buffer is disabled when the sequencer reaches the step en32k_step on the way down. 7.9.6 power - down disable the pd_dis_step pointer can be used to define a step in the power - up sequence above which a group of functions will be enabled. the functions concerned can be controlled in the pd_dis register. similarly, in the power - down sequence, the same groups of functions will be disabled when the sequencer proceeds below the pd_dis_step. 7.10 junction temperature supervision to protect da9062 - a fr om damage due to excessive power dissipation , the junction temperature is continuously monitored. the monitoring is split into three thresholds t warn (125 c), t crit (140 c), and t por (150 c). if the junction temperature rises above the first threshold ( t warn ), the event e_temp is asserted. if the event is not masked, this will issue an interrupt. this first level of temperature supervision is intended for non - invasive temperature control, where the necessary measures for cooling the system down are left to the host software. if the junction temperature increases even further and crosses the second threshold (t crit ) , the temperature error flag temp_crit (in register fault_log) is issued and a shutdown sequence to reset mode is triggered, see s ection 7.8.3 . the nreset output is asserted at the beginning of the shutdown sequence. therefore, the second level of the temperature supervision does not rely on the hos t software to take counter - measures. the fault flag can be evaluated by the application after the next power - up. there is also a third temperature threshold (t por ) which causes da9062 - a to enter reset mode without any sequencing and stop all functions except the rtc. this prevents possible permanent damage due to fast temperature increases. 7.11 system supply voltage supervision two comparators supervise the system supply v sys . one is monitor ing the under - voltage level (v dd_fault_lower ) and the other is indicating a good system supply (v dd_fault_upper ). the v dd_fault_lower threshold is otp configurable and can be set via the vdd_fault_adj control from 2.5 v to 3.25 v in 50 mv steps. the v dd_fa ult_upper threshold is also otp configurable and can be set via the vdd_hyst_adj control from 100 mv to 45 0 mv higher than the v dd_fault_lower threshold. v sys dropping below the v dd_fault_upper threshold asserts the event e_vdd_warn. if the event is not ma sked, this will issue an interrupt, which can be used by the host processor as an indication to
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 50 of 93 ? 2017 dialog semiconductor decrease its activity. the status can also be signaled with a dedicated nvdd_fault signal , see s ection 7.3.2.1 . if v sys drops below v dd_fault_lower , the supply error flag vdd_fault (in register fault_log) is asserted and a shutdown sequence to reset mode is triggered , see s ection 7.8.3 . the nreset output is asserted at the beginning of the shutdown sequence. 7.12 backup battery charger the backup battery charger is designed to charge l ithium - m anganese coin cell batteries and super capacitors. the charger provides a constant charge current with a programmable target voltage. the charging current is programmable from 100 a to 1000 a in 100 a steps and from 1 ma to 6 ma in 1 ma steps. the e nd - of - charge termination voltage is programmable in 100/200 mv steps from 1.1 v to 3.1 v. when enabled, the charger will always keep the backup battery charged at its target voltage. the backup battery charger can be tempora ri ly disabled in powerdown mode via control bbat_dis . the backup battery charger includes a reverse current protection and can also be used as an always - on supply for low - power rails. the backup battery provides an internal supply voltage for the 32 khz crystal oscillator and rtc. 7.13 real - time clock the real time clock ( rtc ) provides a real - time clock and alarm function that can be supplied from the backup battery. rtc mode is described in s ection 7.8.2 . the rtc counter will count the number of 32 khz clock periods, providing a seconds, minutes, hours, days, months, and years output . year 0 corresponds to 2000. it is able to count up to 63 years. the value of the rtc calendar is read - and writeable via the 2 - wire interface. a read of count_s (seconds) saves the current rtc calendar count into registers count_s to count_y. registers are only valid when the rtc_read status bit is asserted (assertion may take several ms from leaving por). after monitor has been set, host writing to cry stal and rtc_en is prohibited to ensure that the rtc registers second_a to second_d are never stopped. there is an alarm register containing min, hrs, day, month, and year. when the rtc counter register value corresponds to the value set in the alarm an in terrupt and a wake - up event are generated. the trigger will also set a bit in an event register to notify that an alarm has occurred. the alarm can alternatively be asserted from a periodic tick signal that, depending on control tick_type, is either assert ed every second or minute. after modifying tick_type or tick_wake, a write to register alarm_y is required to activate the new settings. the power manager controls , alarm_on and tick_on , enable/disable the alarm/tick. the power manager register bit monito r is set to 0 each time the rtc is powered up. software sets this bit to 1 when setting the time and date, which allows detection of a subsequent loss of the clock. values written to the rtc calendar and alarm registers have to comply with the allowed valu e range (see register description, for example, less than 60 for seconds or minutes). 7.13.1 32 kh z crystal oscillator the oscillator is used to drive the rtc counter. it works with an external piezoelectric oscillator crystal at 32 k hz. the oscillator output c an be fed to a gpio and used as a clock source in the platform. the buffer can be enabled/disabled from a control register or with the power sequencer. in order to achieve the desired crystal frequency an external capacitor (10 pf to 20 pf, depending on th e parasitic capacitance of the board) is connected to ground from each of the crystal pins. the start - up time of the oscillator is typically between 0.5 s and 1 s over the voltage range. when the crystal is not mounted , the xtal pins should be grounded. th e oscillator can be enabled from control crystal. a stabili z ation timer can be used to blank the clock output during the start - up. the timer can be started simultaneously with the oscillator or it can be configured to wait until the clocks duty cycle is w ithin the range 30 % to 70 %. the start is configured from the delay_mode control and the stabili z ation time is programmed in the
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 51 of 93 ? 2017 dialog semiconductor stabilisation_time control . out_clock controls whether the clock feed to the out_32k output (gpio) is affected by the stabiliz ation timer. the rtc_clock control provides a similar gating function for the clock feed to the internal rtc counter. the clock feed to the out_32k output can be controlled with the power sequencer, as described in s ection 7.9.5 . in addition, the clock output is one of the features that can be disabled in the powerdown mode, as described in s ection 7.9.6 . when the out32k_pause control is set, the clock output is disabled in powerdown . 7.14 internal oscillator an internal oscillator provides a nominal 6.0 mhz clock that is divided to 3.0 mhz for th e buck converters. the frequency of the internal oscillator is adjusted during the initial start - up sequence of da9062 - a to within 5 % of the nominal 6.0 mhz. some applications require that the software is able to modify the oscillator frequency at runt ime, for example to avoid interference effects caused by harmonics of the buck converter operating frequency. this can be achieved by writing a non - zero value to control osc_frq . this control is a signed 4 - bit value where each step changes the frequency by about 1.33 %, which gives a range from - 10.65 % ( - 8) to +9.33 % (+7). the tolerance of this frequency will affect most absolute timer values and pwm repetition rates. 7.15 watchdog the watchdog provides system monitoring functionality. a watchdog timeout trigg er s shutdown to powerdown mode , signaled in register fault_log . the watchdog can also be configured to control a secondary reset output in addition to nreset. this requires that one of the gpios is configured as a gpo, controlled by the sequencer. the asse rtion/de - assertion is used as a reset, and the gpio is configured as a sequencer controlled gpo. this way, after the watchdog triggers the power - down, the reset output is asserted by the sequencer during the power - down sequence. once enabled, the watchdog cannot be stopped and it runs in active mode (this feature can be bypassed with an otp configuration). the source clock of the watchdog is automatically chosen between the 32 khz clock generated from the crystal oscillator and an internally generated slow frequency clock. after a cold boot, the watchdog is activated when entering active mode . this first watchdog kick is required for da9062 - a to move to the active mode after a cold boot, as illustrated in figure 20 . after the watchdog is activated, the host must kick the watchdog periodically within the watchdog period programmed with the twdscale control . an interrupt can be generated to warn the host processor of the watchdog timeout . the time for the warning interrupt is half of the watchdog period. the kick can be done by a register write to control watchdog ( register control_f) or with the gpio0 pin configured as a wdkick input. with control wdg_mo de = 1, the behavior of the wdkick input is modified so that either a pulse or a permanently asserted input prevents a watchdog timeout . in this mode the parameter t wdmin is not applicable. if the host processor fails to feed the watchdog, da9062 - a asser t s a fault bit and enter s powerdown mode. the watchdog timeout can also be configured to assert a reset output. this requires that one of the gpios is configured as a reset output and assigned to a po wer sequencer step, see section 7.9 . after each watchdog timeout a retry counter is decremented. if the retry counter reaches zero, da9062 - a will stay in powerdown mode, as described in s ection 7.8.4 . the number of allowed retries can be programmed in the nfreeze control .
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 52 of 93 ? 2017 dialog semiconductor 8 register map 8.1 register page control the device register map is larger than the addres s range directly addressable from the host interface. th e page control register provides the higher address bits and control for using the paging mechanism. there are several copies of this register, one per host interface. t hese copies are mirrored to add resses 0x080, 0x100 and 0x180. 8.2 overview table 29 provides a summary of the registers. a description of each register is provided in appendix a . table 29 : register summary addr ess name 7 6 5 4 3 2 1 0 page control 0x000 page_con revert write_mode page power manager control and monitoring 0x001 status_a rese r ved dvc_busy rese r ved nonkey 0x002 status_b rese r ved gpi4 gpi3 gpi2 gpi1 gpi0 0x004 status_d rese r ved ldo4_ilim ldo3_ilim ldo2_ilim ldo1_ilim 0x005 fault_log wait_shut nresetreq key_reset temp_crit vdd_start vdd_fault por twd_error irq events 0x006 event_a rese r ved events_c events_b e_seq_rdy e_wdg_warn rese r ved e_alarm e_nonkey 0x007 event_b e_vdd_warn rese r ved e_dvc_rdy rese r ved e_ldo_lim rese r ved e_temp rese r ved 0x008 event_c rese r ved e_gpi4 e_gpi3 e_gpi2 e_gpi1 e_gpi0 irq masks 0x00a irq_mask_a rese r ved m_seq_rdy m_wdg_warn rese r ved m_alarm m_nonkey 0x00b irq_mask_b m_vdd_warn rese r ved m_dvc_rdy rese r ved m_ldo_lim rese r ved m_temp rese r ved 0x00c irq_mask_c rese r ved m_gpi4 m_gpi3 m_gpi2 m_gpi1 m_gpi0 system c ontrol 0x00e control_a rese r ved m_power1_en m_power_en m_system_en standby power1_en power_en system_en 0x00f control_b buck_slowst art nfreeze nonkey_lock nres_mode freeze_en watchdog_pd rese r ved 0x010 control_c def_supply slew_rate otpread_en auto_boot debouncing 0x011 control_d rese r ved twdscale 0x012 control_e v_lock rese r ved rtc_en rtc_mode_sd rtc_mode_pd 0x013 control_f rese r ved wake_up shutdown watchdog 0x014 pd_dis pmcont_dis out32k_pause bbat_dis cldr_pause rese r ved pmif_dis rese r ved gpi_dis gpio c ontrol 0x015 gpio_0_1 gpio1_wen gpio1_type gpio1_pin gpio0_wen gpio0_type gpio0_pin 0x016 gpio_2_3 gpio3_wen gpio3_type gpio3_pin gpio2_wen gpio2_type gpio2_pin 0x017 gpio_4 rese r ved gpio4_wen gpio4_type gpio4_pin 0x01c gpio_wkup_ mode rese r ved gpio4_wkup_m ode gpio3_wkup_m ode gpio2_wkup_mo de gpio1_wkup_mo de gpio0_wkup_mod e 0x01d gpio_mode0_ 4 rese r ved gpio4_mode gpio3_mode gpio2_mode gpio1_mode gpio0_mode 0x01e gpio_out0_2 gpio2_out gpio1_out gpio0_out 0x01f gpio_out3_4 rese r ved gpio4_out gpio3_out power s upply c ontrol 0x020 buck2_cont rese r ved vbuck2_gpi rese r ved buck2_conf buck2_gpi buck2_en 0x021 buck1_cont rese r ved vbuck1_gpi rese r ved buck1_conf buck1_gpi buck1_en 0x022 buck4_cont rese r ved vbuck4_gpi rese r ved buck4_conf buck4_gpi buck4_en 0x024 buck3_cont rese r ved vbuck3_gpi rese r ved buck3_conf buck3_gpi buck3_en 0x026 ldo1_cont ldo1_conf vldo1_gpi rese r ved ldo1_pd_dis ldo1_gpi ldo1_en 0x027 ldo2_cont ldo2_conf vldo2_gpi rese r ved ldo2_pd_dis ldo2_gpi ldo2_en 0x028 ldo3_cont ldo3_conf vldo3_gpi rese r ved ldo3_pd_dis ldo3_gpi ldo3_en 0x029 ldo4_cont ldo4_conf vldo4_gpi rese r ved ldo4_pd_dis ldo4_gpi ldo4_en 0x032 dvc_1 vldo4_sel vldo3_sel vldo2_sel vldo1_sel vbuck3_sel vbuck4_sel vbuck2_sel vbuck1_sel
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 53 of 93 ? 2017 dialog semiconductor addr ess name 7 6 5 4 3 2 1 0 rtc c alendar and a larm 0x040 count_s rtc_read rese r ved count_sec 0x041 count_mi rese r ved count_min 0x042 count_h rese r ved count_hour 0x043 count_d rese r ved count_day 0x044 count_mo rese r ved count_month 0x045 count_y rese r ved monitor count_year 0x046 alarm_s alarm_status alarm_sec 0x047 alarm_mi rese r ved alarm_min 0x048 alarm_h rese r ved alarm_hour 0x049 alarm_d rese r ved alarm_day 0x04a alarm_mo rese r ved tick_wake tick_type alarm_month 0x04b alarm_y tick_on alarm_on alarm_year 0x04c second_a seconds_a 0x04d second_b seconds_b 0x04e second_c seconds_c 0x04f second_d seconds_d power s equencer 0x081 seq reserved seq_pointer 0x082 seq_timer seq_dummy seq_time 0x083 id_2_1 ldo2_step ldo1_step 0x084 id_4_3 ldo4_step ldo3_step 0x088 id_12_11 pd_dis_step rese r ved 0x089 id_14_13 buck2_step buck1_step 0x08a id_16_15 buck3_step buck4_step 0x08d id_22_21 gp_fall1_step gp_rise1_step 0x08e id_24_23 gp_fall2_step gp_rise2_step 0x08f id_26_25 gp_fall3_step gp_rise3_step 0x090 id_28_27 gp_fall4_step gp_rise4_step 0x091 id_30_29 gp_fall5_step gp_rise5_step 0x092 id_32_31 en32k_step wait_step 0x095 seq_a power_end system_end 0x096 seq_b part_down max_count 0x097 wait wait_dir time_out wait_mode wait_time 0x098 en_32k en_32kout rese r ved out_clock delay_mode crystal stabilisation_time 0x099 reset reset_event reset_timer power s upply c ontrol 0x09a buck_ilim_a rese r ved buck3_ilim 0x09b buck_ilim_b rese r ved buck4_ilim 0x09c buck_ilim_c buck2_ilim buck1_ilim 0x09d buck2_cfg buck2_mode buck2_pd_dis rese r ved 0x09e buck1_cfg buck1_mode buck1_pd_dis rese r ved 0x09f buck4_cfg buck4_mode buck4_pd_dis buck4_vtt_en buck4_vttr_e n rese r ved 0x0a0 buck3_cfg buck3_mode buck3_pd_dis rese r ved 0x0a3 vbuck2_a buck2_sl_a vbuck2_a 0x0a4 vbuck1_a buck1_sl_a vbuck1_a 0x0a5 vbuck4_a buck4_sl_a vbuck4_a 0x0a7 vbuck3_a buck3_sl_a vbuck3_a 0x0a9 vldo1_a ldo1_sl_a rese r ved vldo1_a 0x0aa vldo2_a ldo2_sl_a rese r ved vldo2_a 0x0ab vldo3_a ldo3_sl_a rese r ved vldo3_a 0x0ac vldo4_a ldo4_sl_a rese r ved vldo4_a 0x0b4 vbuck2_b buck2_sl_b vbuck2_b 0x0b5 vbuck1_b buck1_sl_b vbuck1_b 0x0b6 vbuck4_b buck4_sl_b vbuck4_b 0x0b8 vbuck3_b buck3_sl_b vbuck3_b 0x0ba vldo1_b ldo1_sl_b rese r ved vldo1_b 0x0bb vldo2_b ldo2_sl_b rese r ved vldo2_b 0x0bc vldo3_b ldo3_sl_b rese r ved vldo3_b 0x0bd vldo4_b ldo4_sl_b rese r ved vldo4_b
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 54 of 93 ? 2017 dialog semiconductor addr ess name 7 6 5 4 3 2 1 0 bbat c harger c ontrol 0x0c5 bbat_cont bchg_iset bchg_vset customer trim and configuration 0x105 interface if_base_addr rese r ved 0x106 config_a rese r ved pm _if_hsm pm _if_fmp pm _if_v irq_type pm_o_type rese r ved pm_i_v 0x107 config_b rese r ved vdd_hyst_adj vdd_fault_adj 0x108 config_c rese r ved buck3_clk_inv rese r ved buck4_clk_inv buck1_clk_inv buck_actv_disc hrg rese r ved 0x109 config_d rese r ved force_reset rese r ved system_en_rd nirq_mode gpi_v 0x10a config_e rese r ved buck3_auto rese r ved buck4_auto buck2_auto buck1_auto 0x10c config_g rese r ved ldo4_auto ldo3_auto ldo2_auto ldo1_auto 0x10d config_h rese r ved buck1_fcm buck2_fcm rese r ved buck_merge rese r ved 0x10e config_i ldo_sd int_sd_mode host_sd_mode key_sd_mode watchdog_sd n onkey_sd nonkey_pin 0x10f config_j if_reset twowire_to reset_duration shut_delay key_delay 0x110 config_k rese r ved gpio4_pupd gpio3_pupd gpio2_pupd gpio1_pupd gpio0_pupd 0x112 config_m osc_frq wdg_mode rese r ved rese r ved rese r ved customer device specific 0x121 gp_id_0 gp_0 0x122 gp_id_1 gp_1 0x123 gp_id_2 gp_2 0x124 gp_id_3 gp_3 0x125 gp_id_4 gp_4 0x126 gp_id_5 gp_5 0x127 gp_id_6 gp_6 0x128 gp_id_7 gp_7 0x129 gp_id_8 gp_8 0x12a gp_id_9 gp_9 0x12b gp_id_10 gp_10 0x12c gp_id_11 gp_11 0x12d gp_id_12 gp_12 0x12e gp_id_13 gp_13 0x12f gp_id_14 gp_14 0x130 gp_id_15 gp_15 0x131 gp_id_16 gp_16 0x132 gp_id_17 gp_17 0x133 gp_id_18 gp_18 0x134 gp_id_19 gp_19 0x181 device_id dev_id 0x182 variant_id mrc vrc 0x183 customer_i d cust_id 0x184 config_id config_rev
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 55 of 93 ? 2017 dialog semiconductor 9 application information 9.1 component selection the following recommended components are examples selected from requirements of a typical application. the final component selection will be dependent on the specific application. the electrical characteristics (for example, supported voltage/current range) have to be cross - checked and component types may need to be adapted from the individual needs of the target circuitry. 9.1.1 resistors ta ble 30 : recommended resistors pin value tol. size ( mm ) r ating ( m w) part iref 200 k 1 % 1005 100 panasonic erj2rkf2003x 9.1.2 capacitors ceramic capacitors are used as bypass capacitors at all vdd and output rails. when selecting a capacitor, especially ones with high capacitance and small size, the dc bias characteristic has to be taken into account. on the vsys main supply rail, a minimu m distributed capacitance of 40 f (actual capacitance after voltage and temperature derating) is required. buck input capacitors should be within 1.5 mm distance from the supply pin, and the output capacitor should be close to the inductor. table 31 : recommended capacitors pin value tol. size ( mm ) height ( mm ) temp. char. rating ( v ) part vldo1 1 f 1 0% 1005 0.55 x5r 10 grm155r61a105ke15 vldox 2.2 f 2 0 % 1005 0.55 x5r 10 grm155r60j225me95# vbuck3 i out 1.5 a 2 x 22 f 20% 2012 0.95 x5r 6.3 grm219r60j226m*** 20% 1005 0.5 x5r 4.0 cl05a226mr5nznc vbuck3 i out > 1.5 a 2 x 47 f 20% 2012 0.95 x5r 4.0 grm219r60g476m*** 20% 1608 0.8 x5r 4.0 cl10a476mr8nzn vbuck4 2 x 22 f 20% 1608 1 x5r 6.3 grm188r60j226mea0 20% 1005 0.5 x5r 4.0 cl05a226mr5nznc vbuck4 (vtt mode) 2 x 47 f 20% 2012 0.95 x5r 4.0 grm219r60g476m***61 20% 1608 0.8 x5r 4.0 cl10a476mr8nzn vbuck1, vbuck2 (half - current mode) 2 x 22 f 20% 1608 1 x5r 6.3 grm188r60j226mea0 20% 1005 0.5 x5r 4.0 cl05a226mr5nznc vbuck1, vbuck2 (full - current mode) 2 x 47 f 20% 2012 0.95 x5r 4.0 grm219r60g476m***61 20% 1608 0.8 x5r 4.0 cl10a476mr8nzn vsys 1 x 1 f 10% 1005 0.5 x5r 10 grm155r61a105ke15d vdd_buckx 2 x 22 f 20% 2012 1.25 x5r 10 lmk212bj226mg - t 4 x 10 f 20% 1005 0.5 x5r 10 grm155r61a106me21
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 56 of 93 ? 2017 dialog semiconductor pin value tol. size ( mm ) height ( mm ) temp. char. rating ( v ) part vdd_ldo2 1 x 1 f 10% 1005 0.5 x5r 10 grm155r61a105ke15d vdd_ldo34 1 x 1 f 10% 1005 0.5 x5r 10 grm155r61a105ke15d vbbat 470 nf 10% 1005 0.55 x5r 10 grm155r61a474ke15# vddcore, vref 2.2 f 20% 1005 0.55 x5r 6.3 grm155r60j225me95# xtal_in , xtal_out 12 pf 5% 1005 0.55 u2j 50 grm1557u1h120jz01# 9.1.3 inductors inductors should be selected based upon the following parameters: i sat specifies the current causing a reduction in the inductance by a specific amount, typically 30 % i rms specifies the current causing a temperature rise of a specific amount dc resistance (dcr) is critical for converter efficiency and should be therefore mi nim ize d. esr at the buck switching frequency is critical to converter efficiency in pfm mode and should be therefore minim ize d. inductance is given in table 32 . table 32 : recommended inductors buck value isat ( a ) irms ( a ) dcr (typ . m ? ) size (w l h ) m m part buck1 and buck2 (half - current mode), buck3, buck4 1 h 2.7 2.3 55 2.0 1.6 1.0 toko 1285as - h - 1r0 m 2.65 2.45 60 2.0 1.6 1.0 tayo yuden makk2016t1r0m 2.9 2.2 60 2.0 1.6 1.0 tdk tfm201610a - 1r0m buck4 (vtt mode) 0.24 h 1.65 2.3 43 1.6 0.81.0 taiyo yuden mbkk1608tr24n 0.2 5 h 9.7 11.45 7.64 4.0 4.0 1.2 coilcraft xfl4012 - 251me buck1, buck 2 (full - current mode) 1 h 3.4 3 60 2.5 2.0 1.0 toko1269as - h - 1r0 m 3.6 3.1 45 2.5 2.0 1.2 tayo yuden mamk2520t1r0m 3.8 3.5 45 2.5 2.0 1.2 toko 1239as - h - 1r0 m 3.9 3.1 48 3.2 2.5 1.0 toko1276as - h - 1r0 m 3.5 2.5 54 2.5 2.0 1.0 tdk tfm252010a - 1r0m 3.35 2.5 52 3.0 3.0 1.2 cyntec pst031b - 1r0ms 5.4 11 10.8 4.0 4.0 2.1 coilcraft xfl4020 - 102me 9.1.4 crystal the rtc module requires an external 32.768 khz crystal. for correct component selection, the effective load capacitance must to be taken into account. this includes external capacitors on pins xtal_in and xtal_out in series combination, plus the pcb and stray capacitances. for example, if two 12 pf external capacitors are used, resulting in a total capacitance of 6 pf, and assuming the stray capacitances are 3 pf, then a crystal that specifies a load capacitance of 9 pf should be
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 57 of 93 ? 2017 dialog semiconductor chosen. different stray capacitances may require different external capacitors and/or a different crystal type. furthermore, the series resistance of the crystal must not exceed 100 k ? . table 33 : recommended crystal type size (w l h ) mm manufacturer cc7v - t1a 32.768 khz 9.0 pf 30 ppm 3.2 1.5 0.9 micro crystal 9.1.5 backup battery the backup battery charger supports lithium coin cells as well as supercaps/goldcaps. table 34 : recommended backup battery type size ( mm ) manufacturer lithium battery (rechargeable) ml414, 1.0 mah, 3.1 v 4.8 ( ?), 1.4 (h) sanyo, panasonic starcap sc sm 2r8, 0.1 f, 2.8 v 4.8 ( ? ), 1.4 (h) korchip electric double layer capacitor (gold capacitor) eecep0e333a, 0.033 f, 2.6 v 3.8 ( ? ), 1.5 (h) panasonic 9.2 pcb layout figure 23 : pcb layout for da9062 - a 1 0 0 5 1 0 0 5 1 0 0 5 1 0 0 5 2 0 1 6 2 0 1 6 l x 2 g n d v b b a t v b u c k 4 c m 7 v - t 1 a 1 0 0 5 1 0 0 5 1 0 0 5 1 0 0 5 v l d o 4 s d a s c l n o n k e y n r e s e t r e q v l x b u c k 4 v d d b u c k 4 v d d b u c k 3 v l x b u c k 3 g p i o 0 g p i o 1 v d d i o v b u c k 4 g p i o 4 v b u c k 3 v b u c k 1 v b u c k 2 g p i o 2 g p i o 3 v l x b u c k 1 v d d b u c k 1 v d d b u c k 2 v l x b u c k 2 v l x b u c k 2 t p n i r q n r s t v d d c o r e v s y s v l d o 1 v l d o 2 v d d l d o 2 i r e f v r e f x i n v s s a n a x o u t v l d o 3 v d d l d o 3 4 v b u c k 3 1 6 0 8 1 6 0 8 1 0 0 5 1 0 0 5 1 0 0 5 2 0 1 6 1 0 0 5 1 0 0 5 1 0 0 5 1 0 0 5 2 0 1 6 1 6 0 8 l x 1 q u i e t g r o u n d q u i e t g r o u n d
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 58 of 93 ? 2017 dialog semiconductor 9.2.1 general recommendations appropriate trace width and quantity of vias should be used for all power supply paths. too high trace resistances can prevent the system from achieving the best performance, f or example, the efficiency and the current ratings of switching converters might be degraded. furthermore, the pcb may be exposed to thermal hot spots, which can lead to critical overheating due to the positive temperature coefficient of copper. special ca re must be taken with the da9062 - a pad connections. the traces connecting the pads should of the same width as the pads and they should become wider as soon as possible. it is recommended to create a separate quiet ground to which the vref capacitor, ir ef resistor, and the crystal capacitors are connected. the pcb layout should ensure these component grounds are kept quiet, that is, they should be separated from the main ground return path for the noisy power ground. the quiet ground can then be connected to the main ground at the paddle, as shown in figure 23 . all traces carrying high discontinuous currents should be kept as short as possible. noise sensitive analog signals, such as feedback lines or crystal connections, should be kept away from traces carrying pulsed analog or di gital signals. this can be achieved by separation or shielding with quiet signals or ground traces. 9.2.2 ldos and switched mode supplies the placement of the distributed capacitors on the vsys rail must ensure that all vdd inputs and vsys are connected to a byp ass capacitor close to the pad. it is recommended placing at least two 1 f capacitors close to the vdd_ldox pads and at least one 10 f close to the vdd_buckx pads. using a local power plane underneath the device for vsys might be considered. transient cu rrent loops in the area of the switching converters should be minim ize d. the common references (iref, vref) should be placed close to the device and cross - coupling to any noisy digital or analog trace must be avoided. output capacitors of the ldos can be p laced close to the input pins of the supplied devices (remote from the da9062 - a ). care must be taken with trace routing to ensure that no current is carried on feedback lines of the buck output voltages (vbuckx). the inductor placement is less critical since parasitic inductances have negligible effect. 9.2.3 32 khz c rystal oscillator the crystal and its load capacitors should be placed as close as possible to the ic with short and symmetric al traces. the traces must be isolated from noisy signals, especially from clocked digital ones. ideally the lines should be buried between two ground layers, surrounded by additional ground traces. 9.2.4 optim izing thermal performance da9062 - a features a ground paddle which should be connected with as many vias as possible to the pcbs main ground plane in order to achieve good thermal performance. solder mask openings for the ball landing pads must be arranged to prohibit solder balls flowing into vias.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 59 of 93 ? 2017 dialog semiconductor 10 ordering information the order ing number consists of the part number fol lowed by a suffix indicating the packing method. the xx represents a placeholder for the specific otp variant. for details and availability , please consult dialogs customer portal or your local sales representa tive. table 35 : ordering information part number package (mm) package description comment da9062 - a - xxam1 qfn40, 6 x 6 tray, 490 pcs da9062 - a - xxam1 - a qfn40, 6 x 6 tray, 490 pcs automotive aec - q100 grade 3 da9062 - a - xxam2 qfn40, 6 x 6 t&r, 4000 pcs da9062 - a - xxam2 - a qfn40, 6 x 6 t&r, 4000 pcs automotive aec - q100 grade 3
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 60 of 93 ? 2017 dialog semiconductor appendix a register descriptions this appendix describes the registers summarized in s ection 8 . a.1 page 0 a.1.1 page control table 36 : page_con (0x000) field bit type description revert 7:7 r/w 0: page switches the regmap page until rewritten. 1: page reverts to 0 after one access. write_mode 6:6 r/w 2 - wire sequential write style. 0: write data to consecutive addresses 1: write data to random addresses using address/data pairs page 5:0 r/w the top 6 bits of the register address. for 2 - wire, page[0] is ignored. a.1.2 power m anager control and monitoring table 37 : status_a (0x001) field bit type description reserved 7:3 r reserved dvc_busy 2:2 r one or more dvc capable supplies are ramping reserved 1:1 r reserved nonkey 0:0 r nonkey level table 38 : status_b (0x002) field bit type description reserved 7:5 r reserved gpi4 4:4 r gpi 4 level gpi3 3:3 r gpi 3 level gpi2 2:2 r gpi 2 level gpi1 1:1 r gpi 1 level gpi0 0:0 r gpi 0 level table 39 : status_d (0x004) field bit type description reserved 7:4 r reserved ldo4_ilim 3:3 r ldo 4 over - current indicator ldo3_ilim 2:2 r ldo 3 over - current indicator ldo2_ilim 1:1 r ldo 2 over - current indicator ldo1_ilim 0:0 r ldo 1 over - current indicator
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 61 of 93 ? 2017 dialog semiconductor table 40 : fault_log (0x005) field bit type description wait_shut 7:7 r no te 1 power - down due to sequencer wait _step timeout. see s ection 7.9.4 for further infor mation. nresetreq 6:6 r note 1 power - down due to nresetreq pin or control shutdown. key_reset 5:5 r note 1 power - down due to nonkey temp_crit 4:4 r note 1 junction over - temperature vdd_start 3:3 r note 1 power - down due to vsys under - voltage before or within 16 sec onds after release of nreset. vdd_fault 2:2 r note 1 power - down due to vsys under - voltage. por 1:1 r note 1 da9062 - a starts up from no - power or rtc / delivery mode. twd_error 0:0 r note 1 watchdog timeout note 1 cleared from the host by writing back the read value. a.1.3 irq events table 41 : event_a (0x006) field bit type description reserved 7:7 r reserved events_c 6:6 r event in register event_c is active. events_b 5:5 r event in register event_b is active. e_seq_rdy 4:4 r note 1 sequencer reached final position. e_wdg_warn 3:3 r note 1 watchdog timeout warning e_tick 2:2 r rtc tick e_alarm 1:1 r note 1 rtc a larm e_nonkey 0:0 r note 1 nonkey event note 1 cleared from the host by writing back the read value.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 62 of 93 ? 2017 dialog semiconductor table 42 : event_b (0x007) field bit type description e_vdd_warn 7:7 r note 1 v sys under - voltage ( v sys < v dd_fault_upper ) reserved 6:6 r reserved e_dvc_rdy 5:5 r note 1 all supplies have finished dvc ramping reserved 4:4 r reserved e_ldo_lim 3:3 r note 1 ldo over - current reserved 2:2 r reserved e_temp 1:1 r note 1 junction over - temperature (t j > t warn ) reserved 0:0 r reserved note 1 cleared from the host by writing back the read value. table 43 : event_c (0x008) field bit type description reserved 7:5 r reserved e_gpi4 4:4 r note 1 gpi 4 event e_gpi3 3:3 r note 1 gpi 3 event e_gpi2 2:2 r note 1 gpi 2 event e_gpi1 1:1 r note 1 gpi 1 event e_gpi0 0:0 r note 1 gpi 0 event note 1 cleared from the host by writing back the read value. a.1.4 irq masks table 44 : irq_mask_a (0x00 a ) field bit type description reserved 7:5 r/w reserved m_seq_rdy 4:4 r/w irq mask for s equencer final position indication (e_seq_rdy) m_wdg_warn 3:3 r/w irq mask for w atchdog timeout warning (e_wdg_warn) m_tick 2:2 r/w irq mask for rtc tick event (e_tick) m_alarm 1:1 r/w irq mask for rtc a larm (e_alarm) m_nonkey 0:0 r/w irq mask for nonkey event (e_nonkey)
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 63 of 93 ? 2017 dialog semiconductor table 45 : irq_mask_b (0x00 b ) field bit type description m_vdd_warn 7:7 r/w irq mask for under - voltage event (e_vdd_warn) v sys < v dd_fault_upper reserved 6:6 r / w reserved m_dvc_rdy 5:5 r/w all supplies have finished dvc ramping. reserved 4:4 r / w reserved m_ldo_lim 3:3 r/w irq mask for ldo over - current event (e_ldo_lim) reserved 2:2 r / w reserved m_temp 1:1 r/w irq mask for j unction over - temperature event (e_temp) reserved 0:0 r / w reserved table 46 : irq_mask_c (0x00 c ) field bit type description reserved 7:5 r/w reserved m_gpi4 4:4 r/w irq mask for gpi4 event (e_gpi4) m_gpi3 3:3 r/w irq mask for gpi3 event (e_gpi3) m_gpi2 2:2 r/w irq mask for gpi2 event (e_gpi2) m_gpi1 1:1 r/w irq mask for gpi1 event (e_gpi1) m_gpi0 0:0 r/w irq mask for gpi0 event (e_gpi0) a.1.5 system control table 47 : control_a (0x00 e ) field bit type description reserved 7:7 r/w reserved m_power1_en 6:6 r/w write mask for power1_en m_power_en 5:5 r/w write mask for power_en m_system_en 4:4 r/w write mask for system_en standby 3:3 r/w clearing control system_en or releasing sys_en (gpio4 alternate function) or a long press of nonkey will : 0: p ower - down to slot 0. 1: power - down as far as defined by the part_down pointer . power1_en 2:2 r/w target status of power domain power1. bus write masked with m_power1_en. power_en 1:1 r/w target status of power domain power. bus write masked with m_power_en. system_en 0:0 r/w target status of power domain system. bus write masked with m_system_en.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 64 of 93 ? 2017 dialog semiconductor table 48 : control_b (0x00 f ) field bit type description buck_slowstart 7:7 r/w enable buck slow start (reduced inrush current; increased start - up time). nfreeze 6:5 r/w block all wake - up s after nfreeze watchdog restart trials. nonkey_lock 4:4 r/w 0: normal powerdown mode 1: power - down controlled by key_delay nres_mode 3:3 r/w if powering down / up : 0: k eep nreset not asserted 1: a ssert / clear nreset when entering / leaving powerdown freeze_en 2:2 r/w enable watchdog restart limit nfreeze. watchdog_pd 1:1 r/w watchdog timer is on (1) / off (0) in powerdown mode. reserved 0:0 r/w reserved table 49 : control_c (0x010) field bit type description def_supply 7:7 r/w 1: otp enables / disables all supplies (except ldocore) when sequencer enters slot 0. slew_rate 6:5 r/w buck dvc slew rate step width [ 10 mv/step (20 mv/step for buck3)] 0 0 : 4 s 0 1: 2 s 10 : 1 s 11 : 0.5 s otpread_en 4:4 r/w when leaving powerdown mode supplies are configured from otp. auto_boot 3:3 r/w after progressing from reset mode , the sequencer: 0: requires a wake - up event to start up. 1: starts up automatically. debouncing 2:0 r/w gpi, nonkey and nresetreq debounce time 000 : no debouncing 001 : 0.1 ms 010 : 1.0 ms 011 : 10.24 ms 100 : 51.2 ms 101 : 256 ms 110 : 512 ms 111 : 1024 ms table 50 : control_d (0x011) field bit type description reserved 7:3 r/w reserved twdscale 2:0 r/w watchdog timeout scaling : 0: watchdog disabled o ther: timeout = 2.5 * 2^(twdscale - 1) s
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 65 of 93 ? 2017 dialog semiconductor table 51 : control_e (0x012) field bit type description v_lock 7:7 r/w prevent host from writing to registers 0x81 - 0x120 except 0x100. reserved 6: 3 r/w reserved rtc_en 2:2 r/w enable real time clock and a larm. rtc_mode_sd 1:1 r/w disable all supplies and blocks and ldocore if psm enters reset mode . rtc_mode_pd 0:0 r/w disable all supplies and blocks and ldocore if psm enters powerdown mode . table 52 : control_f (0x013) field bit type description reserved 7:3 r/w reserved wake_up 2:2 r/w wake - up from powerdown mode. cleared automatically. shutdown 1:1 r/w power - down to reset mode. cleared automatically. watchdog 0:0 r/w reset watchdog timer. cleared automatically. table 53 : pd_dis (0x014) field bit type description pmcont_dis 7:7 r/w disable sys_en, pwr_en and pwr1_en in powerdown mode. out32k_pause 6:6 r/w disable out _ 32k in powerdown mode. bbat_dis 5:5 r/w disable backup battery charger in powerdown mode. cldr_pause 4:4 r/w disable calendar update in powerdown mode. reserved 3:3 r/w reserved pmif_dis 2:2 r/w disable 2 - wire interface in powerdown mode. reserved 1:1 r/w reserved gpi_dis 0:0 r/w disable e_gpi < x > events in powerdown mode.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 66 of 93 ? 2017 dialog semiconductor a.1.6 gpio control table 54 : gpio_0_1 (0x015) field bit type description gpio1_wen 7:7 r/w 0: passive - to - active transition triggers wake up . 1: no wake up gpio1_type 6:6 r/w gpi: active high (1) / low (0) gpio1_pin 5:4 r/w function of gpio 1 pin (see gpio1_out if output) 00 : reserved 01 : input (opt. regul. hw ctrl.) 10 : output (open drain) 11 : output (push - pull) gpio0_wen 3:3 r/w 0: passive - to - active transition triggers wake up . 1: no wake up gpio0_type 2:2 r/w gpi: active high (1) / low (0) gpio0_pin 1:0 r/w function of gpio 0 pin (see gpio 0 _out if output) 00 : watchdog trigger input 01 : i nput 10 : o utput (open drain) 11 : o utput (push - pull) table 55 : gpio_2_3 (0x016) field bit type description gpio3_wen 7:7 r/w 0: passive - to - active transition triggers wake up . 1: no wake up gpio3_type 6:6 r/w gpi: active high (1) / low (0) gpio3_pin 5:4 r/w function of gpio 3 pin (see gpio3_out if output) 00 : reserved 01 : input (opt. regul. hw ctrl.) 10 : output (open drain) 11 : output (push - pull) gpio2_wen 3:3 r/w 0: passive - to - active transition triggers wake up . 1: no wake up gpio2_type 2:2 r/w gpi: active high (1) / low (0) gpio2_pin 1:0 r/w function of gpio 2 pin (see gpio 2 _out if output) 00 : gpi as pwr _en 01 : i nput (opt. regul. hw ctrl.) 10 : o utput (open drain) 11 : n vdd_fault
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 67 of 93 ? 2017 dialog semiconductor table 56 : gpio_4 (0x017) field bit type description reserved 7:4 r/w reserved gpio4_wen 3:3 r/w 0: passive - to - active transition triggers wake up . 1: no wake up gpio4_type 2:2 r/w gpi: active high (1) / low (0) gpio4_pin 1:0 r/w function of gpio pad (see gpio 4 _out if output) 00 : gpi as sys_en 01 : i nput 10 : o utput (open drain) 11 : o utput (push - pull) table 57 : gpio_wkup_mode (0x01 c ) field bit type description reserved 7:5 r/w reserved gpio4_wkup_mode 4:4 r/w gpi 4 wake up is edge (0) / level (1) sensitive. gpio3_wkup_mode 3:3 r/w gpi 3 wake up is edge (0) / level (1) sensitive. gpio2_wkup_mode 2:2 r/w gpi 2 wake up is edge (0) / level (1) sensitive. gpio1_wkup_mode 1:1 r/w gpi 1 wake up is edge (0) / level (1) sensitive. gpio0_wkup_mode 0:0 r/w gpi 0 wake up is edge (0) / level (1) sensitive. table 58 : gpio_mode0_4 (0x01 d ) field bit type description reserved 7:5 r/w reserved gpio4_mode 4:4 r /w output, static: the output value output, other: active low (0) / high (1) input: debouncing off (0) / on (1) gpio3_mode 3:3 r /w output, static: the output value output, other: active low (0) / high (1) input: debouncing off (0) / on (1) gpio2_mode 2:2 r /w output, static: the output value output, other: active low (0) / high (1) input: debouncing off (0) / on (1) gpio1_mode 1:1 r /w output, static: the output value output, other: active low (0) / high (1) input: debouncing off (0) / on (1) gpio0_mode 0:0 r /w output, static: the output value output, other: active low (0) / high (1) input: debouncing off (0) / on (1)
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 68 of 93 ? 2017 dialog semiconductor table 59 : gpio_out0_2 (0x01 e ) field bit type description gpio2_out 7:6 r /w gpio output function 00 : static value according gpio 2 _mode 01 : n vdd_fault 10 : 32 khz crystal clock (out_32k) 11 : sequencer controlled gpio1_out 5:3 r /w gpio output function 000 : static value according gpio1_mode 001 : n vdd_fault 010 : 32 khz crystal clock (out_32k) 011 : sequencer controlled 100 : forward gpi0 101 : r eserved 110 : forward gpi2 111 : forward gpi3 gpio0_out 2:0 r /w gpio output function 000 : static value according gpio0_mode 001 : n vdd_fault 010 : 32 khz crystal clock (out_32k) 011 : sequencer controlled 100 : r eserved 101 : forward gpi1 110 : forward gpi2 111 : forward gpi3 table 60 : gpio_out3_4 (0x01 f ) field bit type description reserved 7:5 r /w reserved gpio4_out 4:3 r /w gpio output function 00 : static value according gpio 4 _mode 01 : n vdd_fault 10 : 32 khz crystal clock (out_32k) 11 : sequencer controlled gpio3_out 2:0 r /w gpio output function 000 : static value according gpio3 _mode 001 : n vdd_fault 010 : 32 khz crystal clock (out_32k) 011 : sequencer controlled 100 : forward gpi0 101 : forward gpi1 110 : forward gpi2 111 : r eserved
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 69 of 93 ? 2017 dialog semiconductor a.1.7 power supply control table 61 : buck2_cont (0x020) field bit type description reserved 7:7 r /w reserved vbuck2_gpi 6:5 r /w voltage controlling gpi (passive to active transition: vb*_b, act. to pas.: vb*_a) reserved 4:4 r /w reserved buck2_conf 3:3 r /w default supply, or sequenced and on in powerdown buck2_gpi 2:1 r /w enabling gpi (passive to active transition: enable, act. to pas.: disable) buck2_en 0:0 r /w disable (0) / enable (1) the buck (dependent on on/off priority order), except in buck 1/2 dual - phase mode table 62 : buck1_cont (0x021) field bit type description reserved 7:7 r/w reserved vbuck1_gpi 6:5 r/w voltage controlling gpi (passive to active transition: vb*_b, act. to pas.: vb*_a) 00 : sequencer controlled 01 : select gpi1 10 : select gpi2 11 : select gpi3 reserved 4:4 r/w reserved buck1_conf 3:3 r/w default supply, or sequenced and on in powerdown buck1_gpi 2:1 r/w enabling gpi (passive to active transition: enable, act. to pas.: disable) 00 : sequencer controlled 01 : select gpi1 10 : select gpi2 11 : select gpi3 buck1_en 0:0 r/w disable (0) / enable (1) the buck (dependent on on/off priority order)
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 70 of 93 ? 2017 dialog semiconductor table 63 : buck4_cont (0x022) field bit type description reserved 7:7 r/w reserved vbuck4_gpi 6:5 r/w voltage controlling gpi (passive to active transition: vb*_b, act. to pas.: vb*_a) 00 : sequencer controlled 01 : select gpi1 10 : select gpi2 11 : select gpi3 reserved 4:4 r/w reserved buck4_conf 3:3 r/w default supply, or sequenced and on in powerdown buck4_gpi 2:1 r/w enabling gpi (passive to active transition: enable, act. to pas.: disable) 00 : sequencer controlled 01 : select gpi1 10 : select gpi2 11 : select gpi3 buck4_en 0:0 r/w disable (0) / enable (1) the buck (dependent on on/off priority order) table 64 : buck3_cont (0x024) field bit type description reserved 7:7 r/w reserved vbuck3_gpi 6:5 r/w voltage controlling gpi (passive to active transition: vb*_b, act. to pas.: vb*_a) 00 : sequencer controlled 01 : select gpi1 10 : select gpi2 11 : select gpi3 reserved 4:4 r/w reserved buck3_conf 3:3 r/w default supply, or sequenced and on in powerdown buck3_gpi 2:1 r/w enabling gpi (passive to active transition: enable, act. to pas.: disable) 00 : sequencer controlled 01 : select gpi1 10 : select gpi2 11 : select gpi3 buck3_en 0:0 r/w disable (0) / enable (1) the buck (dependent on on/off priority order)
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 71 of 93 ? 2017 dialog semiconductor table 65 : ldo1_cont (0x026) field bit type description ldo1_conf 7:7 r/w default supply, or sequenced and on in powerdown vldo1_gpi 6:5 r/w voltage controlling gpi (passive to active transition: vldo*_b, act. to pas.: vldo*_a) 00 : sequencer controlled 01 : select gpi1 10 : select gpi2 11 : select gpi3 reserved 4:4 r/w reserved ldo1_pd_dis 3:3 r/w disable pull - down resistor when disabled. ldo1_gpi 2:1 r/w enabling gpi (passive to active transition: enable, act. to pas.: disable) 00 : sequencer controlled 01 : select gpi1 10 : select gpi2 11 : select gpi3 ldo1_en 0:0 r/w disable (0) / enable (1) the ldo (dependent on on/off priority order) table 66 : ldo2_cont (0x027) field bit type description ldo2_conf 7:7 r/w default supply, or sequenced and on in powerdown vldo2_gpi 6:5 r/w voltage controlling gpi (passive to active transition: vldo*_b, act. to pas.: vldo*_a) 00 : sequencer controlled 01 : select gpi1 10 : select gpi2 11 : select gpi3 reserved 4:4 r/w reserved ldo2_pd_dis 3:3 r/w disable pull - down resistor when disabled. ldo2_gpi 2:1 r/w enabling gpi (passive to active transition: enable, act. to pas.: disable) 00 : sequencer controlled 01 : select gpi1 10 : select gpi2 11 : select gpi3 ldo2_en 0:0 r/w disable (0) / enable (1) the ldo (dependent on on/off priority order)
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 72 of 93 ? 2017 dialog semiconductor table 67 : ldo3_cont (0x028) field bit type description ldo3_conf 7:7 r/w default supply, or sequenced and on in powerdown vldo3_gpi 6:5 r/w voltage controlling gpi (passive to active transition: vldo*_b, act. to pas.: vldo*_a) 00 : sequencer controlled 01 : select gpi1 10 : select gpi2 11 : select gpi3 reserved 4:4 r/w reserved ldo3_pd_dis 3:3 r/w disable pull - down resistor when disabled. ldo3_gpi 2:1 r/w enabling gpi (passive to active transition: enable, act. to pas.: disable) 00 : sequencer controlled 01 : select gpi1 10 : select gpi2 11 : select gpi3 ldo3_en 0:0 r/w disable (0) / enable (1) the ldo (dependent on on/off priority order) table 68 : ldo4_cont (0x029) field bit type description ldo4_conf 7:7 r/w default supply, or sequenced and on in powerdown vldo4_gpi 6:5 r/w voltage controlling gpi (passive to active transition: vldo*_b, act. to pas.: vldo*_a) 00 : sequencer controlled 01 : select gpi1 10 : select gpi2 11 : select gpi3 reserved 4:4 r/w reserved ldo4_pd_dis 3:3 r/w disable pull - down resistor when disabled. ldo4_gpi 2:1 r/w enabling gpi (passive to active transition: enable, act. to pas.: disable) 00 : sequencer controlled 01 : select gpi1 10 : select gpi2 11 : select gpi3 ldo4_en 0:0 r/w disable (0) / enable (1) the ldo (dependent on on/off priority order)
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 73 of 93 ? 2017 dialog semiconductor table 69 : dvc_1 (0x032) field bit type description vldo4_sel 7:7 r/w select vldo4_a (0) / vldo4 _b (1) . vldo3_sel 6:6 r/w select vldo3_a (0) / vldo3_b (1) . vldo2_sel 5:5 r/w select vldo2_a (0) / vldo2_b (1) . vldo1_sel 4:4 r/w select vldo1_a (0) / vldo1_b (1) . vbuck3_sel 3:3 r/w select vbuck3_a (0) / vbuck3_b (1). vbuck4_sel 2:2 r/w select vbuck4_a (0) / vbuck4_b (1). vbuck2_sel 1:1 r/w select vbuck2_a (0) / vbuck2_b (1). vbuck1_sel 0:0 r/w select vbuck1_a (0) / vbuck1_b (1).
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 74 of 93 ? 2017 dialog semiconductor a.1.8 rtc calendar and alarm table 70 : count_s (0x040) field bit type description rtc_read 7:7 r indicates that rtc calendar is ready to be read by the host. reserved 6:6 r reserved count_sec 5:0 r/w calendar seconds bus write is snapshot and updated on a write to count_year. bus read loads rtc calendar into 0x104 - 0x109. table 71 : count_mi (0x041) field bit type description reserved 7 :6 r reserved count_min 5:0 r/w calendar minutes 0 - 59 bus write is snapshot and updated on a write to count_year. bus read is snapshot and updated on a read from count_sec. table 7 2 : count_h (0x042) field bit type description reserved 7:5 r reserved count_hour 4:0 r/w calendar hours 0 - 23 bus write is snapshot and updated on a write to count_year. bus read is snapshot and updated on a read from count_sec. table 73 : count_d (0x043) field bit type description reserved 7:5 r reserved count_day 4:0 r/w calendar day s 1 - 31 bus write is snapshot and updated on a write to count_year. bus read is snapshot and updated on a read from count_sec. table 74 : count_mo (0x044) field bit type description reserved 7: 4 r reserved count_month 3:0 r/w calendar month s 1 - 12 bus write is snapshot and updated on a write to count_year. bus read is snapshot and updated on a read from count_sec.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 75 of 93 ? 2017 dialog semiconductor table 75 : count_y (0x045) field bit type description reserved 7: 7 r reserved monitor 6:6 r/w read: rtc power has been lost (0) / rtc clock okay (1). write: rtc_en and crystal writing enabled (0) / disabled (1). fetched from vddrtc domain at vddcore por. if set, host writes to this register are ignored; thus the host cannot clear it. count_year 5:0 r/w calendar year 2000 - 2063 bus write turns on the rtc clock and sets rtc cale ndar. bus read is snapshot and updated on a read from count_sec. table 76 : alarm_s (0x046) field bit type description alarm_status 7:6 r alarm reason 00 : no alarm 01 : tick 10 : timer 11 : tick + timer alarm_sec 5:0 r/w alarm seconds 0 - 59 bus write is snapshot and updated on a write to alarm_year. table 77 : alarm_mi (0x047) field bit type description reserved 7:6 r reserved alarm_min 5:0 r/w alarm minutes 0 - 59 bus write is snapshot and updated on a write to alarm_year. table 78 : alarm_h (0x048) field bit type description reserved 7:5 r reserved alarm_hour 4:0 r/w alarm hour s 0 - 23 bus write is snapshot and updated on a write to alarm_year. table 79 : alarm_d (0x049) field bit type description reserved 7:5 r reserved alarm_day 4:0 r/w alarm day s 1 - 31 bus write is snapshot and updated on a write to alarm_year.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 76 of 93 ? 2017 dialog semiconductor table 80 : alarm_mo (0x04 a ) field bit type description reserved 7: 6 r reserved tick_wake 5:5 r/w allows a tick to wake the chip from rtc mode tick_type 4:4 r/w tick p eriod 0: every second 1: every minute alarm_month 3:0 r/w alarm month s 1 - 12 bus write is snapshot and updated on a write to alarm_year. table 81 : alarm_y (0x04 b ) field bit type description tick_on 7:7 r/w enable the tick function. alarm_on 6:6 r/w enable the alarm function. alarm time is set with the alarm_* registers alarm_year 5:0 r/w alarm year s 2000 - 2063 table 82 : second_a (0x04 c ) field bit type description seconds_a 7:0 r rtc seconds counter least significant byte table 83 : second_b (0x04 d ) field bit type description seconds_b 7:0 r rtc seconds counter byte bus read is snapshot and updated on a read from seconds_a. table 84 : second_c (0x04 e ) field bit type description seconds_c 7:0 r rtc seconds counter byte bus read is snapshot and updated on a read from seconds_a. table 85 : second_d (0x04 f ) field bit type description seconds_d 7:0 r rtc seconds counter most significant byte bus read is snapshot and updated on a read from seconds_a.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 77 of 93 ? 2017 dialog semiconductor a.2 page 1 a.2.1 power supply sequencer table 86 : seq (0x081) field bit type description reserved 7:4 r/w reserved seq_pointer 3:0 r actual power sequencer position table 87 : seq_timer (0x082) field bit type description seq_dummy 7:4 r/w waiting time for power sequencer slots which do not have an associated power supply. 0000 : 32 s 0001 : 64 s 0010 : 96 s 0011 : 128 s 0100 : 160 s 0101 : 192 s 0110 : 224 s 0111 : 256 s 1000 : 288 s 1001 : 384 s 1010 : 448 s 1011 : 512 s 1100 : 1.024 ms 1101 : 2.048 ms 1110 : 4.096 ms 1111 : 8.192 ms seq_time 3:0 r/w length of each sequencer time slot 0000 : 32 s 0001 : 64 s 0010 : 96 s 0011 : 128 s 0100 : 160 s 0101 : 192 s 0110 : 224 s 0111 : 256 s 1000 : 288 s 1001 : 384 s 1010 : 448 s 1011 : 512 s 1100 : 1.024 ms 1101 : 2.048 ms 1110 : 4.096 ms 1111 : 8.192 ms
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 78 of 93 ? 2017 dialog semiconductor table 88 : id_2_1 (0x083) field bit type description ldo2_step 7:4 r/w sequencer step for ldo2 ldo1_step 3:0 r/w sequencer step for ldo1 table 89 : id_4_3 (0x084) field bit type description ldo4_step 7:4 r/w sequencer step for ldo4 ldo3_step 3:0 r/w sequencer step for ldo3 table 90 : id_12_11 (0x088) field bit type description pd_dis_step 7:4 r/w sequencer step for pd_dis register functionality. reserved 3:0 r/w reserved table 91 : id_14_13 (0x089) field bit type description buck2_step 7:4 r/w sequencer step for buck2 buck1_step 3:0 r/w sequencer step for buck1 table 92 : id_16_15 (0x08 a ) field bit type description buck3_step 7:4 r/w sequencer step for buck3 buck4_step 3:0 r/w sequencer step for buck4 table 93 : id_22_21 (0x08 d ) field bit type description gp_fall1_step 7:4 r/w sequencer step to de - assert gpo 0 gp_rise0_step 3:0 r/w sequencer step to assert gpo 0 table 94 : id_24_23 (0x08 e ) field bit type description gp_fall2_step 7:4 r/w sequencer step to de - assert gpo 1 gp_rise1_step 3:0 r/w sequencer step to assert gpo 1 table 95 : id_26_25 (0x08 f ) field bit type description gp_fall3_step 7:4 r/w sequencer step to de - assert gpo 2 gp_rise2_step 3:0 r/w sequencer step to assert gpo 2
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 79 of 93 ? 2017 dialog semiconductor table 96 : id_28_27 (0x090) field bit type description gp_fall4_step 7:4 r/w sequencer step to de - assert gpo 3 gp_rise3_step 3:0 r/w sequencer step to assert gpo 3 table 97 : id_30_29 (0x091) field bit type description gp_fall5_step 7:4 r/w sequencer step to de - assert gpo 4 gp_rise4_step 3:0 r/w sequencer step to assert gpo 4 table 98 : id_32_31 (0x092) field bit type description en32k_step 7:4 r/w sequencer step to enable gpo and rtc clock wait_step 3:0 r/w sequencer step for wait register functionality table 99 : seq_a (0x095) field bit type description power_end 7:4 r/w end of power power domain in the sequencer system_end <= power_end <= max_count must be true. system_end 3:0 r/w end of system power domain in the sequencer part_down <= system_end <= power_end must be true. table 100 : seq_b (0x096) field bit type description part_down 7:4 r/w s equencer slot to stop at , when going down into standby state. 1 <= part_down <= system_end must be true. max_count 3:0 r/w end of power1 power domain in the sequencer power_end <= max_count must be true.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 80 of 93 ? 2017 dialog semiconductor table 101 : wait (0x097) field bit type description wait_dir 7:6 r/w wait _ step power sequence selection 00 : do not wait during wait_step of power sequencer except for normal slot time. 01 : wait during up sequence. 10 : wait during down sequence. 11 : wait during up and down sequence. time_out 5:5 r/w timeout when wait_mode = 0 0: no timeout when waiting for external signal (gpio3). 1: 500 ms timeout when waiting for external signal (gpio3). wait_mode 4:4 r/w 0: wait for external signal (gpio3) to be active. 1: start timer and wait for expiration. wait_time 3:0 r/w wait timer during wait step of power sequencer (+/ - 10%) 0000 : do not wait during wait_step of power sequencer except for normal slot time. 0001 : 512 s 0010 : 1.0 ms 0011 : 2.0 ms 0100 : 4.1 ms 0101 : 8.2 ms 0110 : 16.4 ms 0111 : 32.8 ms 1000 : 65.5 ms 1001 : 128 ms 1010 : 256 ms 1011 : 512 ms 1100 : 1 .0 s 1101 : 2.0 s 1110 : 4.1 s 1111 : 8.2 s
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 81 of 93 ? 2017 dialog semiconductor table 102 : en_32k (0x098) field bit type description en_32kout 7:7 r/w enable out_32k on the gpos (may be del ayed depending on out32k_pause) rtc_clock 6:6 r/w disable clock to rtc counter until stabilization timer has expired. out_clock 5:5 r/w disable clock to gpos configured as out_32k until stabili z ation timer has expired. delay_mode 4:4 r/w start stabili z ation timer : 0: when oscillator signal is available ( thi rd falling edge) 1: when oscillator has been switched on (crystal risen ) crystal 3:3 r/w external rtc crystal is present. fetched from vddrtc domain at vddcore por. stabilisation_time 2:0 r/w time to allow crystal oscillator to stabil ize . 000 : delay off 001 : 0.52 s 010 : 1.0 s 011 : 1.5 s 100 : 2.1 s 101 : 2.6 s 110 : 3.1 s 111 : 3.6 s table 103 : reset (0x099) field bit type description reset_event 7:6 r/w reset timer started by: 00 : ext_wakeup 01 : sys_up (register control or pin) 10 : pwr_up (register control or pin) 11 : leaving pmic reset mode reset_timer 5:0 r/w 0: release nreset immediately after the event selected by reset_event. 1 - 31: 1.024 ms * reset_timer 32 - 63: 1.024 ms * 32 * (reset_timer - 31)
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 82 of 93 ? 2017 dialog semiconductor a.2.2 power supply control table 104 : buck_ilim_a (0x09 a ) field bit type description reserved 7:4 r/w reserved buck3_ilim 3:0 r/w buck 3 current limit = ( 17 00 + buck3_ilim * 100) ma table 105 : buck_ilim_b (0x09 b ) field bit type description reserved 7:4 r/w reserved buck4_ilim 3:0 r/w buck 4 current limit = ( 7 00 + buck4_ilim * 100) ma table 106 : buck_ilim_c (0x09 c ) field bit type description buck2_ilim 7:4 r/w buck 2 current limit = ( 7 00 + buck2_ilim * 100) ma in full - current mode the limit is internally doubled. buck1_ilim 3:0 r/w buck 1 current limit = ( 7 00 + buck1_ilim * 100) ma in full - current mode the limit is internally doubled. table 107 : buck2_cfg (0x09 d ) field bit type description buck2_mode 7:6 r/w controls the mode of the buck: 00: controlled by buck2_sl_a and buck2_sl_b 01: sleep (pfm) 10: synchronous (pwm) 11: automatic buck2_pd_dis 5:5 r/w disable pull - down resistor when disabled. reserved 4:0 r/w reserved table 108 : buck1_cfg (0x09 e ) field bit type description buck1_mode 7:6 r/w controls the mode of the buck: 00: controlled by buck1_sl_a and buck1_sl_b 01: sleep (pfm) 10: synchronous (pwm) 11: automatic buck1_pd_dis 5:5 r/w disable pull - down resistor when disabled. reserved 4:1 r/w reserved reserved 0:0 r/w reserved
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 83 of 93 ? 2017 dialog semiconductor table 109 : buck4_cfg (0x09 f ) field bit type description buck4_mode 7:6 r/w controls the mode of the buck: 00: controlled by buck4_sl_a and buck4_sl_b 01: sleep (pfm) 10: synchronous (pwm) 11: automatic buck4_pd_dis 5:5 r/w disable pull - down resistor when disabled. buck4_vtt_en 4:4 r/w enable buck4 memory bus termination mode. buck4_vttr_en 3:3 r/w enable buck4 memory bus termination reference voltage output. reserved 2:0 r/w reserved table 110 : buck3_cfg (0x0 a 0) field bit type description buck3_mode 7:6 r/w controls the mode of the buck: 00: controlled by buck3_sl_a and buck3_sl_b 01: sleep (pfm) 10: synchronous (pwm) 11: automatic buck3_pd_dis 5:5 r/w disable pull - down resistor when disabled. reserved 4:0 r/w reserved table 111 : vbuck2_a (0x0 a 3) field bit type description buck2_sl_a 7:7 r/w this control is only effective when buck2_mode = 0 0: forced to synchronous mode (pwm) when 'a' setting is active. 1: forced to sleep mode (pfm) when 'a' setting is active. vbuck2_a 6:0 r/w from 0.3 v (0x00) to 1.57 v (0x7f) in steps of 10 mv table 112 : vbuck1_a (0x0 a 4) field bit type description buck1_sl_a 7:7 r/w this control is only effective when buck1_mode = 0 0: forced to synchronous mode (pwm) when 'a' setting is active. 1: forced to sleep mode (pfm) when 'a' setting is active. vbuck1_a 6:0 r/w from 0.3 v (0x00) to 1.57 v (0x7f) in steps of 10 mv table 113 : vbuck4_a (0x0 a 5) field bit type description buck4_sl_a 7:7 r/w this control is only effective when buck4_mode = 0 0: forced to synchronous mode (pwm) when 'a' setting is active. 1: forced to sleep mode (pfm) when 'a' setting is active. vbuck4_a 6:0 r/w from 0.53 v (0x00) to 1.8 v (0x7f) in steps of 10 mv
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 84 of 93 ? 2017 dialog semiconductor table 114 : vbuck3_a (0x0 a 7) field bit type description buck3_sl_a 7:7 r/w this control is only effective when buck3_mode = 0 0: forced to synchronous mode (pwm) when 'a' setting is active. 1: forced to sleep mode (pfm) when 'a' setting is active. vbuck3_a 6:0 r/w from 0.80 v (0x00) to 3.34 v (0x7f) in steps of 20 mv table 115 : vldo1_a (0x0 a 9) field bit type description ldo1_sl_a 7:7 r/w force ldo sleep mode if vldo 1 _a is active. reserved 6:6 r/w reserved vldo1_a 5:0 r/w from 0.90 v (0x02) to 3.60 v (0x38) in steps of 50 mv less than 0x02: 0.90 v; greater than 0x38: 3.60 v table 116 : vldo2_a (0x0 aa ) field bit type description ldo2_sl_a 7:7 r/w force ldo sleep mode if vldo 2 _a is selected. reserved 6:6 r/w reserved vldo2_a 5:0 r/w from 0.90 v (0x02) to 3.60 v (0x38) in steps of 50 mv less than 0x02: 0.90 v; greater than 0x38: 3.60 v table 117 : vldo3_a (0x0 ab ) field bit type description ldo3_sl_a 7:7 r/w force ldo sleep mode if vldo 3 _a is selected. reserved 6:6 r/w reserved vldo3_a 5:0 r/w from 0.90 v (0x02) to 3.60 v (0x38) in steps of 50 mv less than 0x02: 0.90 v; greater than 0x38: 3.60 v table 118 : vldo4_a (0x0 ac ) field bit type description ldo4_sl_a 7:7 r/w force ldo sleep mode if vldo 4 _a is selected. reserved 6:6 r/w reserved vldo4_a 5:0 r/w from 0.90 v (0x02) to 3.60 v (0x38) in steps of 50 mv less than 0x02: 0.90 v; greater than 0x38: 3.60 v table 119 : vbuck2_b (0x0 b 4) field bit type description buck2_sl_b 7:7 r/w this control is only effective when buck2_mode = 0 0: forced to synchronous mode (pwm) when 'b' setting is active. 1: forced to sleep mode (pfm) when 'b' setting is active. vbuck2_b 6:0 r/w from 0.3 v (0x00) to 1.57 v (0x7f) in steps of 10 mv
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 85 of 93 ? 2017 dialog semiconductor table 120 : vbuck1_b (0x0 b 5) field bit type description buck1_sl_b 7:7 r/w this control is only effective when buck1_mode = 0 0: forced to synchronous mode (pwm) when 'b' setting is active. 1: forced to sleep mode (pfm) when 'b' setting is active. vbuck1_b 6:0 r/w from 0.3 v (0x00) to 1.57 v (0x7f) in steps of 10 mv table 121 : vbuck4_b (0x0 b 6) field bit type description buck4_sl_b 7:7 r/w this control is only effective when buck4_mode = 0 0: forced to synchronous mode (pwm) when 'b' setting is active. 1: forced to sleep mode (pfm) when 'b' setting is active. vbuck4_b 6:0 r/w from 0.53 v (0x00) to 1.8 v (0x7f) in steps of 10 mv table 122 : vbuck3_b (0x0 b 8) field bit type description buck3_sl_b 7:7 r/w this control is only effective when buck3_mode = 0 0: forced to synchronous mode (pwm) when 'b' setting is active. 1: forced to sleep mode (pfm) when 'b' setting is active. vbuck3_b 6:0 r/w from 0.80 v (0x00) to 3.34 v (0x7f) in steps of 20 mv table 123 : vldo1_b (0x0 ba ) field bit type description ldo1_sl_b 7:7 r/w force ldo sleep mode when b setting is active. reserved 6:6 r/w reserved vldo1_b 5:0 r/w from 0.90 v (0x02) to 3.60 v (0x38) in steps of 50 mv less than 0x02: 0.90 v; greater than 0x38: 3.60 v table 124 : vldo2_b (0x0 bb ) field bit type description ldo2_sl_b 7:7 r/w force ldo sleep mode if vldo 2 _b is selected. reserved 6:6 r/w reserved vldo2_b 5:0 r/w from 0.90 v (0x02) to 3.60 v (0x38) in steps of 50 mv less than 0x02: 0.90 v; greater than 0x38: 3.60 v table 125 : vldo3_b (0x0 bc ) field bit type description ldo3_sl_b 7:7 r/w force ldo sleep mode if vldo 3 _b is selected. reserved 6:6 r/w reserved vldo3_b 5:0 r/w from 0.90 v (0x02) to 3.60 v (0x38) in steps of 50 mv less than 0x02: 0.90 v; greater than 0x38: 3.60 v
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 86 of 93 ? 2017 dialog semiconductor table 126 : vldo4_b (0x0 bd ) field bit type description ldo4_sl_b 7:7 r/w force ldo sleep mode if vldo 4 _b is selected. reserved 6:6 r/w reserved vldo4_b 5:0 r/w from 0.90 v (0x02) to 3.60 v (0x38) in steps of 50 mv less than 0x02: 0.90 v; greater than 0x38: 3.60 v a.2.3 bbat charger control table 127 : bbat_cont (0x0 c 5) field bit type description bchg_iset 7:4 r/w charg ing current setting : 0000: d isabled 0001: 100 a 0010: 200 a 0011: 300 a 0100: 400 a 0101: 500 a 0110: 600 a 0111: 700 a 1000: 800 a 1001: 900 a 1010: 1 ma 1011: 2 ma 1100: 3 ma 1101: 4 ma 1110: 5 ma 1111: 6 ma bchg_vset 3:0 r/w termination voltage setting : 0000: d isabled 0001: 1.1 v 0010: 1.2 v 0011: 1.4 v 0100: 1.6 v 0101: 1.8 v 0110: 2.0 v 0111: 2.2 v 1000: 2.4 v 1001: 2.5 v 1010: 2.6 v 1011: 2 .7 v 1100: 2.8 v 1101: 2.9 v 1110: 3.0 v 1111: 3.1 v
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 87 of 93 ? 2017 dialog semiconductor a.3 page 2 a.3.1 customer trim and configuration table 128 : interface (0x105) field bit type description if_base_addr 7:4 r note 1 2 - wire slave address msbs. the lsbs of the slave address are 000. the complete slave address is then if_base_addr * 2 3 . however, the device also responds to if_base_addr * 2 3 +1. reserved 3:0 r reserved note 1 the interface configuration can only be written/modified for unmarked samples which do not have the control otp_apps_lock asserted/fused. table 129 : config_a (0x106) field bit type description reserved 7:7 r reserved pm _if_hsm 6:6 r/w 2 - wire interface permanently in high speed mode pm _if_fmp 5:5 r/w 2 - wire interface selects fast mode+ timings pm _if_v 4:4 r/w 2 - wire supplied from vddcore (0) / v ddio (1). irq_type 3:3 r/w nirq is active low (0) / high (1). pm_o_type 2:2 r/w nreset and nirq are push pull (0) / open drain (1). reserved 1:1 r/w reserved pm_i_v 0:0 r/w nresetreq, sys_en, pwr_en and keepact supplied from vddcore (0) / v ddio (1). table 130 : config_b (0x107) field bit type description reserved 7:7 r/w reserved vdd_hyst_adj 6:4 r/w n vdd_fault comparator hyster e sis from 100 mv (0x0) to 450 mv (0x7) in 50 mv steps vdd_fault_adj 3:0 r/w n vdd_fault comparator level from 2.5 v (0x0) to 3.25 v (0xf) in 50 mv steps table 131 : config_c (0x108) field bit type description reserved 7:7 r/w reserved buck3_clk_inv 6:6 r/w invert buck 3 clock polarity . reserved 5:5 r/w reserved buck4_clk_inv 4:4 r/w invert buck 4 clock polarity . buck1_clk_inv 3:3 r/w invert buck 1 clock polarity with respect to buck2. buck_actv_dischrg 2:2 r/w enable active discharging of buck rails. reserved 1:0 r/w reserved
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 88 of 93 ? 2017 dialog semiconductor table 132 : config_d (0x109) field bit type description reserved 7: 6 r/w reserved force_reset 5:5 r/w keep nreset always asserted reserved 4:3 r/w reserved system_en_rd 2:2 r/w suppress loading system_en during otp_rd2 nirq_mode 1:1 r/w nirq will be asserted from events during powerdown gpi_v 0:0 r/w gpis, except power manager controls, supplied from vddcore (0) / v ddio (1). table 133 : config_e (0x10 a ) field bit type description reserved 7: 5 r/w reserved buck3_auto 4:4 r/w when powering up, enable and select vb uck3 _a. reserved 3:3 r/w reserved buck4_auto 2:2 r/w e nable and select vb uck4 _a when powering up. buck2_auto 1:1 r/w e nable and select vb uck2 _a when powering up . buck1_auto 0:0 r/w e nable and select vb uck1 _a when powering up . table 134 : config_g (0x10 c ) field bit type description reserved 7: 4 r/w reserved ldo4_auto 3:3 r/w e nable and select vldo 4 _a when powering up . ldo3_auto 2:2 r/w e nable and select vldo 3 _a when powering up . ldo2_auto 1:1 r/w e nable and select vldo 2 _a when powering up . ldo1_auto 0:0 r/w e nable and select vldo 1 _a when powering up . table 135 : config_h (0x10 d ) field bit type description reserved 7:7 r/w reserved buck1_fcm 6:6 r/w buck full - current mode (double pass device and current limit). buck2_fcm 5:5 r/w buck full - current mode (double pass device and current limit). reserved 4:4 r/w reserved buck_merge 3:3 r/w buck1 /2 dual - phase configuration . reserved 2:0 r/w reserved
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 89 of 93 ? 2017 dialog semiconductor table 136 : config_i (0x10 e ) field bit type description ldo_sd 7:7 r/w enable switching off an ldo if an over - current is detected longer than 200 ms. int_sd_mode 6:6 r/w skip seq uencer and dummy slot s on shutdown from internal fault. host_sd_mode 5:5 r/w skip seq uencer and dummy slot s on sh u td o wn from control shutdown or nresetreq pin . key_sd_mode 4:4 r/w enable power - on reset on sh u td o wn from nonkey. watchdog_sd 3:3 r/w enable shutdown instead of power - down on watchdog timeout. n onkey_sd 2:2 r/w enable shutdown via long press of nonkey. nonkey_pin 1:0 r/w nonkey function see section 7.1.1 for further information. table 137 : config_j (0x10 f ) field bit type description if_reset 7:7 r/w enable host interface reset via nresetreq pin twowire_to 6:6 r/w enable 35 ms timeout for 2 - wire interfaces reset_duration 5:4 r/w minimum reset mode duration : 00: 22 ms 01: 100 ms 10: 500 ms 11: 1 s shut_delay 3:2 r/w shutdown delay (+ key_delay) for nonkey key_delay 1:0 r/w nonkey locking threshold table 138 : config_k (0x110) field bit type description reserved 7: 5 r/w reserved gpio4_pupd 4:4 r/w gpi: pull - down enabled open drain gpo: pull - up enabled gpio3_pupd 3:3 r/w gpi: pull - down enabled open drain gpo: pull - up enabled gpio2_pupd 2:2 r/w gpi: pull - down enabled open drain gpo: pull - up enabled gpio1_pupd 1:1 r/w gpi: pull - down enabled open drain gpo: pull - up enabled gpio0_pupd 0:0 r/w gpi: pull - down enabled open drain gpo: pull - up enabled
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 90 of 93 ? 2017 dialog semiconductor table 139 : config_m (0x112) field bit type description osc_frq 7:4 r/w adjust internal oscillator frequency : 1000: - 10.67 % 1111: - 1.33 % 0 000: 0.00 % 0001: +1.33 % 0111: +9.33 % wdg_mode 3:3 r/w activate watchdog halt operation mode. reserved 2:2 r/w reserved reserved 1:1 r/w reserved reserved 0:0 r/w reserved a.3.2 customer d evice s pecific table 140 : gp_id_0 (0x121) field bit type description gp_0 7:0 r/w general purpose register note 1 note 1 initial value at start - up is the otp ini file version number. table 141 : gp_id_1 (0x122) field bit type description gp_1 7:0 r/w general purpose register table 142 : gp_id_2 (0x123) field bit type description gp_2 7:0 r/w general purpose register table 143 : gp_id_3 (0x124) field bit type description gp_3 7:0 r/w general purpose register table 144 : gp_id_4 (0x125) field bit type description gp_4 7:0 r/w general purpose register table 145 : gp_id_5 (0x126) field bit type description gp_5 7:0 r/w general purpose register table 146 : gp_id_6 (0x127) field bit type description gp_6 7:0 r/w general purpose register
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 91 of 93 ? 2017 dialog semiconductor table 147 : gp_id_7 (0x128) field bit type description gp_7 7:0 r/w general purpose register table 148 : gp_id_8 (0x129) field bit type description gp_8 7:0 r/w general purpose register table 149 : gp_id_9 (0x12 a ) field bit type description gp_9 7:0 r/w general purpose register table 150 : gp_id_10 (0x12 b ) field bit type description gp_10 7:0 r/w general purpose register note 1 note 1 the value is persistent through a warm reset such as triggered by the nresetreq pin or by the shutdown control in register control_f. table 151 : gp_id_11 (0x12 c ) field bit type description gp_11 7:0 r/w general purpose register note 1 note 1 the value is persistent through a warm reset such as triggered by the nresetreq pin or by the shutdown control in register control_f. table 152 : gp_id_12 (0x12 d ) field bit type description gp_12 7:0 r/w general purpose register note 1 note 1 the value is persistent through a warm reset such as triggered by the nresetreq pin or by the shutdown control in register control_f. table 153 : gp_id_13 (0x12 e ) field bit type description gp_13 7:0 r/w general purpose register note 1 note 1 the value is persistent through a warm reset such as triggered by the nresetreq pin or by the shutdown control in register control_f. table 154 : gp_id_14 (0x12 f ) field bit type description gp_14 7:0 r/w general purpose register note 1 note 1 the value is persistent through a warm reset such as triggered by the nresetreq pin or by the shutdown control in register control_f.
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 92 of 93 ? 2017 dialog semiconductor table 155 : gp_id_15 (0x130) field bit type description gp_15 7:0 r/w general purpose register note 1 note 1 the value is persistent through a warm reset such as triggered by the nresetreq pin or by the shutdown control in register control_f. table 156 : gp_id_16 (0x131) field bit type description gp_16 7:0 r/w general purpose register note 1 note 1 the value is persistent through a warm reset such as triggered by the nresetreq pin or by the shutdown control in register control_f. table 157 : gp_id_17 (0x132) field bit type description gp_17 7:0 r/w general purpose register note 1 note 1 the value is persistent through a warm reset such as triggered by the nresetreq pin or by the shutdown control in register control_f. table 158 : gp_id_18 (0x133) field bit type description gp_18 7:0 r/w general purpose register note 1 note 1 the value is persistent through a warm reset such as triggered by the nresetreq pin or by the shutdown control in register control_f. table 159 : gp_id_19 (0x134) field bit type description gp_19 7:0 r/w general purpose register note 1 note 1 the value is persistent through a warm reset such as triggered by the nresetreq pin or by the shutdown control in register control_f. table 160 : device _id (0x181 ) field bit type description dev_id 7:0 r device id table 161 : variant _id (0x182 ) field bit type description mrc 7:4 r m ask revision code vrc 3:0 r/w chip v ariant code table 162 : customer _id (0x183 ) field bit type description cust _id 7:0 r customer id table 163 : config _id (0x184 ) field bit type description config_rev 7:0 r otp settings revision
da9062 - a pmic for applications requiring up to 8.5 a datasheet revision 2.0 03 - oct - 2017 cfr0011 - 120 - 00 93 of 93 ? 2017 dialog semiconductor status definitions revision datasheet status product status definition 1. target development this datasheet contains the design specifications for product development. specifications may be changed in any manner without notice. 2. preliminary qualification this datasheet contains the specifications and preliminary characterization data for products in pre - production. sp ecifications may be changed at any time without notice in order to improve the design. 3. final production this datasheet contains the final specifications for products in volume production. the specifications may be changed at any time in order to imp rove the design, manufacturing and supply. major specification changes are communicated via customer product notifications. datasheet changes are communicated via www.dialog - semiconductor.com . 4. ob solete archived this datasheet contains the specifications for discontinued products. the information is provided for reference only. disclaimer information in this document is believed to be accurate and reliable. however, dialog semiconductor does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information. dialog semiconductor furthermore ta kes no responsibility whatsoever for the content in this document if provided by any information sourc e outside of dialog semiconductor. dialog semiconductor reserves the right to change without notice the information published in this document, including withou t limitation the specification and the design of the related semiconductor products, software an d applications. applications, software, and semiconductor products described in this document are for illustrative purposes only. dialog semi conductor makes no representation or warranty that such applications, software and semiconductor products will be suitable for the specified use without further testing or modification. unless otherwise agreed in writing, such testing or modification is the sole responsibility of the c ustomer and dialog semiconductor excludes all liability in this respect. this dialo g semiconductor product has been qualified for use in automotive applications. unless otherwise agreed in writing, the produc t is not designed, authorized or warranted to be suitable for use in life support, life - critical or safety - critical systems or equi pment, nor in applications where failure or malfunction of a dialog semiconductor product can reasonably be expected to result in personal injury, death or severe property or environmental damage. dialog semiconductor and its suppliers accept no liability for inclusion and/or use of dialog semiconductor products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. customer notes that nothing in this document may be construed as a license for customer to us e the dialog semiconductor products, software and applications referred to in this document. such license must be separately sought by customer with dialog semiconductor. all use of dialog semiconductor products, software and applications referred to in th is document are subject to dialog semiconductors standard terms and conditions of sale , available on the company website ( www.dialog - semiconductor.com ) unless otherwise stated. dialog and the dialog logo are trademarks of dialog semiconductor plc or its subsidiaries. all other product or service names are the property of their respective owners. ? 2017 dialog semiconductor. all rights reserved. rohs compliance dialog semiconductors suppliers certify that its products are in compliance with the requirements of directive 2011/65/eu of the european parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. rohs certificates from our suppliers are available on request. contacting dialog semiconductor united kingdom (headquarters) dialog semiconductor (uk) ltd phone: +44 1793 757700 germany dialog semiconductor gmbh phone: +49 7021 805 - 0 the netherlands dialog semiconductor b.v. phone: +31 73 640 8822 north america dialog semiconductor inc. phone: +1 408 845 8500 japan dialog semiconductor k. k. phone: +81 3 5425 4567 taiwan dialog se miconductor taiwan phone: +886 281 786 222 singapore dialog semiconductor singapore phone: +65 64 8499 29 hong kong dialog semiconductor hong kong phone: +852 3769 5200 korea dialog semiconductor korea phone: +82 2 3469 8200 china (shenzhen) dialog semiconductor china phone: +86 755 2981 3669 china (shanghai) dialog semiconductor china phone: +86 21 5424 9058 email: enquiry@diasemi.com web site: www.dialog - semiconductor.com

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